DCD-SEMI Introduces eSPI Combo for Next-Generation Intel-Based Platforms
DESPI eSPI Controller IP Core and DESPI eSPI IP Core Target deliver a complete, high-speed eSPI interface solution for FPGA and ASIC designs.
Vendor:
Digital Core Design
Category:
System Controller
Programmable Peripheral Interface
The D8255 is a programmable I/O device, designed to be used with all Intel CPUs.
Overview
The D8255 is a programmable I/O device, designed to be used with all Intel CPUs. What's significant, it also supports most other microprocessors. Our onnovative IP core provides 24 I/O pins, which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation:
* Mode 0 - Basic Input/Output. This functional configuration provides simple input and output operations for each of the three ports. No ?handshaking'' is required, data is simply written to or read from a specified port. Mode 0 Basic Functional Definitions:
- Two 8-bit ports and two 4-bit ports
- Any port can be input or output
- 16 different Input/Output configurations are possible in this Mode.
* MODE 1 - Strobed Input/Output. This functional configuration provides means for transferring I/O data to or from a specified port in conjunction with strobes or ?handshaking'' signals. In the mode 1, Port A and Port B use the lines on Port C, to generate or accept these ?handshaking'' signals. Mode 1 Basic functional Definitions:
- Two Groups (Group A and Group B).
- Each group contains one 8-bit data port and one 4-bit control/data port.
- The 8-bit data port can be either input or out-put Both inputs and outputs are latched.
- The 4-bit port is used for control and status of the 8-bit data port.
* MODE 2 - Strobed Bidirectional Bus I/O. This functional configuration provides means for communicating with a peripheral device or structure on a single 8-bit bus, both for transmitting and receiving data (bidirectional bus I/O). ?Handshaking'' signals are provided to maintain proper bus flow discipline in a similar manner to the MODE 1. Interrupt generation and enable/disable functions are also available. MODE 2 Basic Functional Definitions:
- Used in Group A only.
- One 8-bit, bi-directional bus port (Port A) and a 5-bit control port (Port C).
- The 5-bit control port (Port C) is used for control and status for the 8-bit, bi-directional bus port (Port A).
The functional configuration of the D8255 is programmed by the system software, so that normally no external logic is needed to interface peripheral devices or structures. The control word register can be both written and read, as it has been shown in the address decode table (please, see the pin descriptions).
* Mode 0 - Basic Input/Output. This functional configuration provides simple input and output operations for each of the three ports. No ?handshaking'' is required, data is simply written to or read from a specified port. Mode 0 Basic Functional Definitions:
- Two 8-bit ports and two 4-bit ports
- Any port can be input or output
- 16 different Input/Output configurations are possible in this Mode.
* MODE 1 - Strobed Input/Output. This functional configuration provides means for transferring I/O data to or from a specified port in conjunction with strobes or ?handshaking'' signals. In the mode 1, Port A and Port B use the lines on Port C, to generate or accept these ?handshaking'' signals. Mode 1 Basic functional Definitions:
- Two Groups (Group A and Group B).
- Each group contains one 8-bit data port and one 4-bit control/data port.
- The 8-bit data port can be either input or out-put Both inputs and outputs are latched.
- The 4-bit port is used for control and status of the 8-bit data port.
* MODE 2 - Strobed Bidirectional Bus I/O. This functional configuration provides means for communicating with a peripheral device or structure on a single 8-bit bus, both for transmitting and receiving data (bidirectional bus I/O). ?Handshaking'' signals are provided to maintain proper bus flow discipline in a similar manner to the MODE 1. Interrupt generation and enable/disable functions are also available. MODE 2 Basic Functional Definitions:
- Used in Group A only.
- One 8-bit, bi-directional bus port (Port A) and a 5-bit control port (Port C).
- The 5-bit control port (Port C) is used for control and status for the 8-bit, bi-directional bus port (Port A).
The functional configuration of the D8255 is programmed by the system software, so that normally no external logic is needed to interface peripheral devices or structures. The control word register can be both written and read, as it has been shown in the address decode table (please, see the pin descriptions).
Key features
- Compatible with industry standard 8255
- 24 I/O lines individually programmed in 2 groups of 12:
- Group A - Port A and upper half of Port C
- Group B - Port B and lower half of Port C
- 3 major modes of operation
- Mode 0 - Basic input/output
- Mode 1 - Strobed Input/output
- Mode 2 - Bi-directional Bus
- Control Word Read-Back Capability
- Direct Bit Set/Reset Capability
- Interrupt control functions
- No internal three states busses
- Fully synthesizable, technology independent source code.
Benefits
- Getting a silicon proven and technologically independent IP (VHDL and Verilog)
- Rapid prototyping and time-to-market reduction
- Design risk elimination
- Development costs reduction
- Full customization
- Wide range of peripherals
- Global sales network
- Professional service
- Fast responsive support
Applications
- Embedded microprocessor boards
- Interface to the printer
- I/O component to interface peripheral
- Equipment to the microcomputer system bus
What’s Included?
- HDL Source Code
- Testbench environment
- Automatic Simulation macros
- Tests with reference responses
- Synthesis scripts
- Technical documentation
- 12 months of technical support
Specifications
Identity
Part Number
D8255
Vendor
Digital Core Design
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Poland
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Frequently asked questions about system controller IP cores
What is Programmable Peripheral Interface?
Programmable Peripheral Interface is a System Controller IP core from Digital Core Design listed on Semi IP Hub.
How should engineers evaluate this System Controller?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this System Controller IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.