PCIe 7.0 PHY, TSMC N3P x4, North/South (vertical) poly orientation

The multi-channel PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and chip-to-chip channels. The PHY’s unique DSP algorithms optimize receiver equalization and the patent-pending diagnostics features enable near zero link downtime. The PHY minimizes package crosstalk, allows dense SoC integration for x16 links, and achieves ultra-low-latency with an optimized data path that is based on an ADC architecture. Support for multiple standards form factors including OCP 3.0, U.2, and U.3 enables serve and storage applications.

The PHY IP for PCIe 7.0 for advanced FinFET processes seamlessly interoperates with the Controller IP for PCIe 7.0 to provide a low-risk solution that designers can use to accelerate time-to-market and efficiently deliver differentiated products that require the 128 GT/s PCIe 7.0 technology.

• Supports the latest features of PCIe® 7.0 specification
• Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
• Unique DSP algorithms deliver more power efficiency across channels
• Patent-pending diagnostic features enable near zero link downtime
• Minimizes package crosstalk with placement-aware architecture
• ADC/DSP based architecture for consistent performance across PVT variation
• Supports lane margining at the receiver
• Supports L0p substate power state
• Power gating and power island
• Embedded bit error rate tester (BERT) and internal eye monitor
• Built-in Self-Test vectors, pseudo random bit sequencer (PRBS) generation and checker
• Supports -40°C to 125°C junction temperatures
• Supports flip-chip packaging