Vendor: Synopsys, Inc. Category: Single-Protocol PHY

PCIe 7.0 PHY, TSMC N2P x4, North/South (vertical) poly orientation

The multi-channel PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across back…

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PCIe Gen7 TSMC 2nm N2P View all specifications

Overview

The multi-channel PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and chip-to-chip channels. The PHY’s unique DSP algorithms optimize receiver equalization and the patent-pending diagnostics features enable near zero link downtime. The PHY minimizes package crosstalk, allows dense SoC integration for x16 links, and achieves ultra-low-latency with an optimized data path that is based on an ADC architecture. Support for multiple standards form factors including OCP 3.0, U.2, and U.3 enables serve and storage applications.

The PHY IP for PCIe 7.0 for advanced FinFET processes seamlessly interoperates with the Controller IP for PCIe 7.0 to provide a low-risk solution that designers can use to accelerate time-to-market and efficiently deliver differentiated products that require the 128 GT/s PCIe 7.0 technology.

Key features

  • Supports the latest features of PCIe® 7.0 specification
  • Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
  • Unique DSP algorithms deliver more power efficiency across channels
  • Patent-pending diagnostic features enable near zero link downtime
  • Minimizes package crosstalk with placement-aware architecture
  • ADC/DSP based architecture for consistent performance across PVT variation
  • Supports lane margining at the receiver
  • Supports L0p substate power state
  • Power gating and power island
  • Embedded bit error rate tester (BERT) and internal eye monitor
  • Built-in Self-Test vectors, pseudo random bit sequencer (PRBS) generation and checker
  • Supports -40°C to 125°C junction temperatures
  • Supports flip-chip packaging

Block Diagram

dwc_pcie7phy_tsmc2p_x4ns block diagram

Silicon Options

Foundry Node Process Maturity
TSMC 2nm N2P —

Specifications

Identity

Part Number
dwc_pcie7phy_tsmc2p_x4ns
Vendor
Synopsys, Inc.
Type
Silicon IP

Standards & Interfaces

Supported Standards
PCIe Gen7

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA
Contact Synopsys, Inc.

Learn more about Single-Protocol PHY IP core

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Industry 1st CXL 4.0 Verification IP: Transforming AI and HPC Systems

Synopsys continues to lead innovation with the industry’s first commercially available CXL 4.0 Verification IP (VIP). This comprehensive solution supports the full 128 GT/s data rate, IO throttling, and streamlined port negotiation, equipping designers to validate and optimize their products for the future.

Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP

In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.

Frequently asked questions about Single-Protocol PHY IP

What is PCIe 7.0 PHY, TSMC N2P x4, North/South (vertical) poly orientation?

PCIe 7.0 PHY, TSMC N2P x4, North/South (vertical) poly orientation is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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