Vendor: T2M GmbH Category: Multi-Protocol PHY

PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 55LL/SP/EF

PCIe Gen 2.0 PHY IP is a physical layer (PHY) IP solution for mobile, consumer and Enterprise applications that enable for a well…

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SMIC 55nm LL In Production View all specifications

Overview

PCIe Gen 2.0 PHY IP is a physical layer (PHY) IP solution for mobile, consumer and Enterprise applications that enable for a well equipped customization and complies with the PCIe2.0 standard specifications while incorporating mixed signal circuits to provide 2.5GT/s and 5.0GT/s data transfer speeds. Physical Media Attachment (PMA) and Physical Coding Sublayer (PCS) are the two levels that make up the PCIe2.0 PHY IP. It simply connects to either the PCIe2.0 MAC layer utilizing the industry-standard PIPE-3.0 interface.
The PCIe2.0 PHY IP transceiver is optimized for low power consumption and small die area while retaining great result and data throughput. The PCIe2.0 PHY IP includes an on-chip physical transceiver solution with ESD protection, a built-in self-test module with inbuilt jitter injection, and a dynamic normalization circuit that ensures full support for high-performance configurations.

Key features

  • Compatible with PCIe base Specification
  • Full compatible with PIPE4.2 interface specification
  • Independent channel power down control
  • Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss
  • Support 16-bit/32bit parallel interface
  • Support for PCIe gen1(2.5Gbps) and PCIe gen2(5.0Gbps)
  • Support flexible reference clock frequency
  • Support 100MHz differential reference clock input or output (with SSC optionally) in PCIe Mode
  • Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm
  • Support programmable transmit amplitude and Deemphasis
  • Support TX detect RX function in PCIe Mode
  • Support Beacon signal generation and detection in
  • Production test support is optimized through high coverage at-speed BIST and loopback
  • Integrated on-die termination resistors and IO Pads/Bumps
  • Embedded Primary & Secondary ESD Protection
  • ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA
  • Silicon Proven in SMIC 55LL/SP/EF

Block Diagram

PCIe 2.0 Serdes PHY IP in 55LL/SP/EF block diagram

What’s Included?

  • GDSII & layer map
  • Place-Route views (.LEF)
  • Liberty library (.lib)
  • Verilog behaviour model
  • Netlist & SDF timing
  • Layout guidelines, application notes
  • LVS/DRC verification reports

Silicon Options

Foundry Node Process Maturity
SMIC 55nm LL In Production

Specifications

Identity

Part Number
PCIe 2.0 Serdes PHY IP in 55LL/SP/EF
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany
Contact T2M GmbH

Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 55LL/SP/EF?

PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 55LL/SP/EF is a Multi-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for smic In Production.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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