PCIe 2.0 PHY, SMIC 28HKMG18 x1, North/South (vertical) poly orientation

The multi-channel PHY IP for PCI Express® 2.1 includes the high-speed, high-performance transceiver to meet today’s demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today’s PCI Express (PCIe®) designs while being extremely low in power and area.

Using the leading-edge design, analysis, simulation, and measurement techniques, the vendor delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standards electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.

The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity, reducing both product development cycles and the need for costly field support.

• Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
• x1, x2, x4, x8, x16 lane configurations with bifurcation
• PCIe L1 substate power management
• Supports power gating and power island
• Embedded bit error rate tester and internal eye monitor
• ATE test vectors for complete, at-speed production testing
• Pseudo random bit sequencer (PRBS) generation and checker
• IEEE 1149.6 AC JTAG Boundry Scan
• Beaconing, receiver detection and electrical idle features
• Supports -40C to 125C junction temperatures