Vendor: Aragio Solutions Category: High-Speed

PCI IO Pad Set

The PCI 3.0 library provides the driver / receiver and required support cells for PCI 3.0 signaling.

GlobalFoundries 28nm SLP Silicon Proven View all specifications

Overview

The PCI 3.0 library provides the driver / receiver and required support cells for PCI 3.0 signaling. The cells are compliant with the PCI Local Bus Specification (Revision 3.0, February 3, 2004) and can be used for both 33 MHz and 66 MHz operation. This library is offered as a supplement to the I/O libraries provided by Aragio Solutions.

What’s Included?

  • a. Physical abstract in LEF format (.lef)
  • b. Timing models in Synopsys Liberty formats (.lib and .db)
  • c. Calibre compatible LVS netlist in CDL format (.cdl)
  • d. GDSII stream (.gds)
  • e. Behavioral Verilog (.v)
  • f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • g. Databook (.pdf)
  • h. Library User Guide - ESD Guidelines (.pdf)

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 28nm SLP Silicon Proven

Specifications

Identity

Part Number
RGO_GF28_18V33_SLP_20C_PCI
Vendor
Aragio Solutions
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about High-Speed IP core

Frequently asked questions about High-Speed I/O Pad IP

What is PCI IO Pad Set?

PCI IO Pad Set is a High-Speed IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for globalfoundries Silicon Proven.

How should engineers evaluate this High-Speed?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this High-Speed IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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