Overview
Certus is pleased to offer Secure Digital compliant IOs in advanced technology nodes. Our SD IOs support DS, HS, SDR25, SDR50, DDR50 and SDR104 protocols. Certus SD solutions are able to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation. Our SD solutions include output enable, a hysteresis receiver, and full interoperability with the feature-rich Certus General-Purpose IO libraries.
Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we consistently exceed the standard ESD targets of 2KV HBM and 500V CDM, but we also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).
Certus also offers RGMII, I2C, SMBUS, DDC, LVDS, Analog/RF, HV and numerous other IO variants across most major foundries and technology nodes. We are particularly suited at providing customized options in a cost-efficient framework. Please contact us for supplementary physical or electrical features that can suit your needs.
Learn more about High-Speed IP core
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