Vendor: M31 Technology Corp. Category: Single-Protocol PHY

ONFI IO v6.0, 4.8GT/s, TSMC N7, 1.2V, N/S orientation, H&V cell

ONFI I/O is a non-volatile memory interface technology with high bandwidth capabilities, mainly developed for flash storage appli…

TSMC 7nm N7 View all specifications

Overview

ONFI I/O is a non-volatile memory interface technology with high bandwidth capabilities, mainly developed for flash storage applications. M31 provides a silicon-proven ONFI I/O in a variety of process nodes, which complies with international Open NAND Flash Interface specification, providing on-die termination (ODT) and supporting ZQ impedance calibration, and can be customized based on customer specifications. The ONFI 6.0, ONFI 5.1, and ONFI 5.0 I/O IP have been silicon-proven at advanced FinFet nodes. In addition, M31 also provides solutions for signal integrity (SI) issues such as FFE and DFE.

Key features

  • Supports ONFI 6.0(4.8Gbps), ONFI 5.1(3.6Gbps), ONFI 5.0(2.4Gbps), ONFI 4.1(1.2Gbps), ONFI 4.0(800Mbps) & ONFI 3.2(533Mbps)
  • Power-sequence free
  • Provides multi-driving-strength selection
  • Provides CTT mode and LTT mode
  • Provides two receivers (Schmitt trigger and LVCMOS receiver) in a cell, which can be selected by the register.
  • Provides ODT (On-Die Termination)
  • Provides ZQ Calibration

Block Diagram

ONFI IO v6.0, 4.8GT/s, TSMC N7, 1.2V, N/S orientation, H&V cell block diagram

Silicon Options

Foundry Node Process Maturity
TSMC 7nm N7 —

Specifications

Identity

Part Number
ONFI IO v6.0, 4.8GT/s, TSMC N7, 1.2V, N/S orientation, H&V cell
Vendor
M31 Technology Corp.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Single-Protocol PHY IP core

M31 Expands Rambus Collaboration, Strengthening Its One-Stop MIPI Subsystem Solution

This collaboration combines these controller capabilities with M31’s silicon-proven MIPI PHY portfolio with a strong track record of successful deployments, enabling M31 to offer a comprehensive MIPI subsystem solution integrating high-speed MIPI PHYs and MIPI CSI/DSI controllers to address the growing requirements of high-resolution imaging and display applications.

M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C

With the rapid growth of AR/VR and high-resolution imaging systems such as drones and action cameras, MIPI CSI (Camera Serial Interface) and MIPI DSI (Display Serial Interface) require both high data throughput and low power consumption. M31 provides a MIPI C-PHY and D-PHY IP combo solution implemented on TSMC N3P and N3C processes.

M31 Gains Momentum in Advanced Processes, Targets Double-Digit Growth in 2026

Consolidated revenue for the first quarter reached NT$395 million, representing a year-over-year decrease of 9.2%. The decline was primarily attributable to timing fluctuations in contract signings for certain key advanced-node customers in North America, with the related revenue expected to be recognized in the second quarter.

Frequently asked questions about Single-Protocol PHY IP

What is ONFI IO v6.0, 4.8GT/s, TSMC N7, 1.2V, N/S orientation, H&V cell?

ONFI IO v6.0, 4.8GT/s, TSMC N7, 1.2V, N/S orientation, H&V cell is a Single-Protocol PHY IP core from M31 Technology Corp. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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