Adapting Foundation IP to Exceed 2 nm Power Efficiency in Next-Gen Hyperscale Compute Engines
Discover how Synopsys Foundation IP helps achieve breakthrough power efficiency in next-gen 2 nm hyperscale compute engines.
Vendor:
Synopsys, Inc.
Category:
CPU
Memory management unit (MMU) option for ARC HS5x and HS6x processors
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
Overview
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where high-performance and high clock speed are required. The processors can be clocked at up to 1.8 GHz in 16FFC processes (worst case, single core, base configuration) and offer outstanding performance delivering 3.0 DMIPS/MHz and 6.16 CoreMark/MHz with a small area footprint and low power consumption.
The ARC HS66 and HS68 processors are based on the advanced ARCv3 instruction set architecture (ISA) and pipeline, which provides leadership power efficiency and code density. The processors feature a 52-bit physical address space and can directly address memories up to 4.5 Petabytes(4.5x1015) in size. For applications requiring higher performance, Multicore Processor (MP) versions of the HS66 and HS68 are available with support for up to 12 HS CPU cores and up to 16 hardware accelerators in the processor cluster.
The ARC HS66 features level 1 (L1) instruction and data cache and closely coupled memory (CCM) and is optimized for use in high-performance real-time embedded applications. The HS68 is designed for use in applications running Linux or SMP Linux. The HS68 has all the features of the HS66 plus support for L2 cache up to 64 MB and a Memory Management Unit (MMU).
To maximize PPA of ARC HS6x-based processor designs, a Fusion QuickStart Implementation Kit (QIK) that includes tool scripts, a baseline floorplan, design constraints and documentation, is available.
Key features
- Dual-issue, 64-bit processors for high-performance embedded applications
- 52-bit physical and 64-bit virtual addressing
- Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
- Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
- Based on advanced ARCv3 ISA
- High degree of configurability
- Enhanced MMU (HS68) with hardware page table walk and up to 16 MB page sizes
- Support for custom instructions
- Support for up to 16 MB of closely coupled memory and direct mapping of peripherals
- Floating Point Unit (FPU) supporting half, single- and double-precision IEEE 754-compliant operation
- ARC Trace Interface provides real-time trace debugging features
- Fusion QuickStart Implementation Kit (QIK) with tool scripts, a baseline floorplan, design constraints and documentation maximizes PPA
- Easy performance upgrade from HS3x and HS4x processors
Block Diagram
dwc_arcv3_hs_mmu_option block diagram
Specifications
Identity
Part Number
dwc_arcv3_hs_mmu_option
Vendor
Synopsys, Inc.
Type
Silicon IP
Compute
CPU Architecture
ARC
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about CPU IP core
PCIe 6.x: Synopsys IP Selected as First Gold System for Compliance Testing
With the Synopsys PCIe 6.x IP solution recently being named the first official “Gold System” for PCIe 6.x compliance testing, the standard is poised to make the leap from promising innovation to practical foundation for future systems and workloads.
The Integrated Design Challenge: Developing Chip, Software, and System in Unison
“We are in an era of pervasive intelligence,” said Shankar Krishnamoorthy, chief product development officer at Synopsys. Moderating a panel discussion at the inaugural Synopsys Executive Forum, he described the transformative impact of artificial intelligence (AI) and the challenges ahead.
Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
With a promise to revolutionize our driving experience, automotive displays are evolving at an unprecedented pace. In modern vehicles, the digital dashboard with a variety of displays that provide access to all driver controls has replaced the physical mechanisms and panels.
How Ultra Ethernet And UALink Enable High-Performance, Scalable AI Networks
This article delves into the technical aspects of how scaling up and out is becoming a critical need for HPC and AI chip developers, and how new standards such as Ultra Ethernet and Ultra Accelerator Link (UALink) aim to tackle the challenges of high-bandwidth, low-latency connectivity and efficient resource management.
Verifying CXL 3.1 Designs with Synopsys Verification IP
Nikhil Jain, Zongyao Wen (Synopsys)
Frequently asked questions about CPU IP cores
What is Memory management unit (MMU) option for ARC HS5x and HS6x processors?
Memory management unit (MMU) option for ARC HS5x and HS6x processors is a CPU IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.