Memory interface IP cores connect processing subsystems to external or embedded memory devices. They include memory controllers, PHYs, controller-plus-PHY subsystems, and interface solutions for DRAM, flash, and high-bandwidth memory technologies.
Browse memory interface IP for DDR, LPDDR, GDDR, HBM, NAND Flash, and NOR Flash with features such as protocol compliance, timing management, ECC, training, low latency, high bandwidth, and process-node optimized PHY integration.
DDR3 and DDR4 Controller and PHY on TSMC 12nm
This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophi…
DDR5/4 PHY V2 in TSMC (N7, N6, N5)
The Synopsys DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications req…
DDR3/ DDR2 Combo PHY IP - 1866Mbps (Silicon Proven in UMC 40LP)
The DDR3/2 PHY is compatible with JEDEC DDR3 and JEDEC DDR2 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to1866Mbps …
DDR4/ DDR3 Combo PHY IP - 2400Mbps (Silicon Proven in UMC 28HPC+)
The DDR4/3 PHY is compatible with JEDEC DDR3 and JEDEC DDR4 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to 2133Mbps…
DDR4/ DDR3/ DDR3L Combo PHY IP - 1600Mpbs (Silicon Proven in TSMC 28HPC+)
This DDR (Double Data Rate) PHY IP supports DDR3/DDR3L/DDR4, provides low latency, and enables up to 1600Mbps throughput.
DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP)
This DDR PHY IP(Double Data Rate) supports DRAM type DDR3, DDR3L this PHY provides low latency, and enables up to 1600Mbps throug…
Highest performance IP for graphics, AI/ML The High-Bandwidth Memory generation 2/2E PHY (HBM2E/2 PHY) is silicon-proven and is a…
VBO TX and RX PHY & Controller
The VBO IP is designed for transmitting or receiving video signals between a video source device and display device, which is ful…
LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as …
TSMC CLN40LPP 40nm LPDDR5 PHY - 3200Mbps
The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically a…
TSMC CLN40LPP 40nm LPDDR4 PHY - 2933Mbps
The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically a…
TSMC CLN40LPP 40nm LPDDR3 PHY - 2133Mbps
The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically a…
TSMC CLN40LPP 40nm DDR5 PHY - 3200Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN40LPP 40nm DDR4 PHY - 2933Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN40LPP 40nm DDR3 PHY - 2133Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN28HPCPLVT 28nm LPDDR5 PHY - 3200Mbps
The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically a…
TSMC CLN28HPCPLVT 28nm LPDDR4 PHY - 2933Mbps
The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically a…
TSMC CLN28HPCPLVT 28nm LPDDR3 PHY - 2133Mbps
The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically a…
TSMC CLN28HPCPLVT 28nm DDR5 PHY - 3200Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN28HPCPLVT 28nm DDR4 PHY - 2933Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…