Vendor: Synopsys, Inc. Category: DDR

DDR5/4 PHY V2 in TSMC (N7, N6, N5)

The Synopsys DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications req…

Controller + PHY + 1 DDR5 TSMC 5nm N5FF View all specifications

Overview

The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR5/4 SDRAM interfaces operating at up to 8400 Mbps. The Synopsys DDR5/4 PHY is ideal for systems that require high- speed, high-performance, and high-capacity memory solutions, typically using registered and load reduced memory modules (RDIMMs and LRDIMMs) with up to 4 physical ranks. Direct SDRAM on PCB systems are also supported.
Optimized for high performance, low latency, low area, low power, and ease of integration, the Synopsys DDR5/4 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR5/4 I/ Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR5/4 PHY. The PUB also includes an embedded calibration processor to execute hardware-assisted, firmware-based training algorithms.
The DDR5/4 PHY includes a DFI 5.0 interface to the memory controller and can be combined with Synopsys’ DDR5/4 controller for a complete DDR interface solution.

Key features

  • Low latency, small area, low power
  • Compatible with JEDEC standard DDR5 SDRAMs up to 8400 Mbps
  • Compatible with JEDEC standard DDR4 SDRAMs up to 3200 Mbps
  • DFI 5.0 compliant interface to the memory controller
  • I/Os include receiver decision feedback equalization (DFE)
  • PHY independent, firmware-based training using an embedded calibration processor
  • Can be trained for up to four distinct states/frequencies to permit fast frequency changes between the four frequencies
  • Three inactive idle states:
  • Voltage and temperature compensated delay lines used for:
  • Supports the following training features:
  • Programmable Read/Write Preamble
  • Includes a low-jitter PLL for both PHY clock generation and SDRAM clock generation
  • Supports PHYs on any side of the die and L-shaped PHYs that go around the die-corner
  • Includes the PHY Utility Block (PUB)
  • At-speed loopback testing on both the address and data channels
  • Delay line BIST and MUX-scan ATPG (stuck-at SCAN)
  • Firmware-based DDR5/4 2D eye mapping diagnostic tool allows measuring 2D eye for every bit of the bus at both DRAM and host receivers

Benefits

  • Supports JEDEC standard DDR5 and DDR4 SDRAMs
  • High-performance DDR PHY supporting data rates up to 8400 Mbps
  • PHY independent, firmware-based training using an embedded calibration processor
  • Supports up to 4 trained states/frequencies with <3us switching time
  • I/O receiver decision feedback equalization
  • VT compensated delay lines for DQS centering, read/write 1D (DDR4) and 2D training (DDR5), and per-bit deskew on both read and write data paths
  • DFI 5.0-compliant controller interface
  • Designed for rapid integration with Synopsys memory controller for a complete DDR interface solution

Applications

  • Data centers (networking and storage)
  • Servers
  • Artificial intelligence/machine learning/ deep learning
  • High-performance computing
  • Digital home
  • Digital office

What’s Included?

  • Executable .run installation file which includes GDSII, LEF files, LVS netlists, .lib/.db timing models, Verilog model, DRC/LVS log files, I/O IBIS Model, I/O HSPICE netlist, parameterized Verilog top-level PHY netlist files, sample Verification Environment, PHY data book, physical implementation guide, app notes, verification guide, installation guide, and implementation checklist
  • PUB includes Verilog code, Synthesis/ STA constraints and scripts, sample verification environment, and data book
  • Implementation Guide, Application notes, and quick start manuals
  • Firmware for training, ATE test and diagnostics
  • DDR PHY compiler
  • Support for PHY emulation
  • Optional deliverables include:
  • Signal integrity consulting services
  • PHY hardening consulting services
  • Subsystems consulting services
  • IP Prototyping kit for FPGA-based prototyping

Silicon Options

Foundry Node Process Maturity
TSMC 5nm N5FF —

Specifications

Identity

Part Number
dwc_ddr54_phy_v2_tsmc
Vendor
Synopsys, Inc.
Type
Silicon IP
Controller / PHY
Controller + PHY , PHY

Standards & Interfaces

Memory
DDR5

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA

Learn more about DDR IP core

Frequently asked questions about DDR Interface IP

What is DDR5/4 PHY V2 in TSMC (N7, N6, N5)?

DDR5/4 PHY V2 in TSMC (N7, N6, N5) is a DDR IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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