The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and…
- Controller + PHY + 1
- LPDDR5
- GlobalFoundries
- 12nm
- LP
- Available on request
LPDDR Interface IP cores provide the controller, PHY, and training technologies required to connect SoCs and ASICs to low-power DRAM, enabling high memory bandwidth while minimizing energy consumption in power-sensitive applications.
This category includes IP solutions supporting LPDDR4, LPDDR5, LPDDR5X, and LPDDR6 memory standards. Available implementations may include memory controllers, PHYs, controller-PHY subsystems, initialization and training engines, power management features, ECC capabilities, and advanced signal integrity technologies optimized for mobile, AI, automotive, and edge computing platforms.
The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and…
LPDDR4x/5 Secondary/Slave (memory side!) PHY
This LPDDR4/4X/5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products.
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
LPDDR6/5X/5 PHY V2 - TSMC N5A for Automotive, ASIL B Random, AEC-Q100 Grade 2
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
LPDDR6/5X/5 PHY V2 - TSMC N3A for Automotive, ASIL B Random, AEC-Q100 Grade 2
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
LPDDR6/5X/5 PHY V2 - Intel 18A-P
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
LPDDR6/5X/5 Controller IP is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC sta…
The DDR PHY is designed to support LPDDR4, LPDDR4x and LPDDR5 SDRAM.
Compatible with JEDEC standards LPDDR4X , LPDDR5 and LPDDR5X SDRAMs; Supports for data transfer rate up to 8533Mbps
LPDDR5/4/4X PHY - TSMC N7 for Automotive, ASIL B Random, AEC-Q100 Grade 2
The LPDDR5/4/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-packag…
The LPDDR5/4/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-packag…