Vendor: Synopsys, Inc. Category: LPDDR

LPDDR6/5X/5 PHY V2 - TSMC N2P

The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…

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Controller + PHY + 1 LPDDR6 TSMC 2nm N2P View all specifications

Overview

The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LPDDR5X, and/or LPDDR5 SDRAM interfaces operating at up to 14.4 Gbps. With flexible configuration options, the LPDDR6/5X/5 PHY IP can be used in a variety of applications supporting LPDDR6, LPDDR5X, and/or LPDDR5 SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems.

LPDDR6 SDRAM’s combination of high bandwidth, capacity, low power, and cost effectiveness makes LPDDR6/5X/5 SDRAMs an attractive solution for traditional and new markets. The LPDDR6/5X/5 PHY IP is designed to appeal to a variety of applications including:

  • Traditional mobile environments
  • Consumer products
  • Automotive solutions
  • Artificial intelligence
  • Data center applications

Key features

  • Support for LPDDR6 with data rates up to 14.4 Gbps, LPDDR5X up to 10.67 Gbps, and LPDDR5 up to 6.4 Gbps
  • Flexible implementation to support discrete DRAM-on-PCB systems, Package-On-Package (PoP), or emerging modules such as LPCAMM2 and SOCAMM
  • Support for East-West and North-South die edge placement, including options to reduce the die edge “beachfront” required for SoCs with many memory interfaces
  • DFI 5.2 compliant controller interface
  • PHY independent, firmware-based training using an embedded calibration processor
  • Support for up to 4 hardware trained states/frequencies
  • I/Os feature transmitter pre-emphasis, time domain DCA, programmable output impedance/slew rate/ODT, and 1 or 2 taps of Decision Feedback Equalization
  • Designed for rapid integration with Synopsys LPDDR5X/5/4X controller IP and verification IP for a complete DDR IP solution

Block Diagram

dwc_lpddr6_phy_v2_tsmc2p block diagram

Silicon Options

Foundry Node Process Maturity
TSMC 2nm N2P —

Specifications

Identity

Part Number
dwc_lpddr6_phy_v2_tsmc2p
Vendor
Synopsys, Inc.
Type
Silicon IP
Controller / PHY
Controller + PHY , PHY

Standards & Interfaces

Memory
LPDDR6

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA
Contact Synopsys, Inc.

Learn more about LPDDR IP core

Frequently asked questions about LPDDR Interface IP

What is LPDDR6/5X/5 PHY V2 - TSMC N2P?

LPDDR6/5X/5 PHY V2 - TSMC N2P is a LPDDR IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this LPDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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