LPDDR6/5X/5 PHY V2 - TSMC N3A for Automotive, ASIL B Random, AEC-Q100 Grade 2

The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LPDDR5X, and/or LPDDR5 SDRAM interfaces operating at up to 14.4 Gbps. With flexible configuration options, the LPDDR6/5X/5 PHY IP can be used in a variety of applications supporting LPDDR6, LPDDR5X, and/or LPDDR5 SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems.

LPDDR6 SDRAM’s combination of high bandwidth, capacity, low power, and cost effectiveness makes LPDDR6/5X/5 SDRAMs an attractive solution for traditional and new markets. The LPDDR6/5X/5 PHY IP is designed to appeal to a variety of applications including:

• Traditional mobile environments
• Consumer products
• Automotive solutions
• Artificial intelligence
• Data center applications

• Support for LPDDR6 with data rates up to 14.4 Gbps, LPDDR5X up to 10.67 Gbps, and LPDDR5 up to 6.4 Gbps
• Flexible implementation to support discrete DRAM-on-PCB systems, Package-On-Package (PoP), or emerging modules such as LPCAMM2 and SOCAMM
• Support for East-West and North-South die edge placement, including options to reduce the die edge “beachfront” required for SoCs with many memory interfaces
• DFI 5.2 compliant controller interface
• PHY independent, firmware-based training using an embedded calibration processor
• Support for up to 4 hardware trained states/frequencies
• I/Os feature transmitter pre-emphasis, time domain DCA, programmable output impedance/slew rate/ODT, and 1 or 2 taps of Decision Feedback Equalization
• Designed for rapid integration with Synopsys LPDDR5X/5/4X controller IP and verification IP for a complete DDR IP solution