Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process
- Controller + PHY + 1
- UMC
- 28nm
- HPC
LPDDR Interface IP cores provide the controller, PHY, and training technologies required to connect SoCs and ASICs to low-power DRAM, enabling high memory bandwidth while minimizing energy consumption in power-sensitive applications.
This category includes IP solutions supporting LPDDR4, LPDDR5, LPDDR5X, and LPDDR6 memory standards. Available implementations may include memory controllers, PHYs, controller-PHY subsystems, initialization and training engines, power management features, ECC capabilities, and advanced signal integrity technologies optimized for mobile, AI, automotive, and edge computing platforms.
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Log…
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process
SMIC 65nm LL DDR3/DDR2/LPDDR2 COMBO interface for DRAM application
IP
SMIC 55nm LL LPDDR interface for DRAM application
IP
IP
SMIC 65nm LL LPDDR interface for mobile-DDR application
IP
IP
IP
DFI3.1 Wrapper for DDR3/DDR4/LPDDR2/LPDDR3 PHY
DFI3.1 Wrapper for DDR3/DDR4/LPDDR2/LPDDR3 PHY
Combo DDR34/LPDDR23 Controller with 8 ports AHB/AXI interfaces
Combo DDR34/LPDDR23 Controller with 8 ports AHB/AXI interfaces