Vendor: Atria Logic, Inc. Category: HMC

Hybrid Memory Cube Verification IP

The IP offers an easy-to-use and complete verification solution for SoC's using the HMC Host Controller at the IP level or system-level.

Verification IP View all specifications

Overview

Atria Logic Hybrid Memory Cube verification IP is a reusable, configurable verification component developed using SystemVerilog. The IP offers an easy-to-use and complete verification solution for SoC's using the HMC Host Controller at the IP level or system-level. The HMC VIP consists of two components:

  • HMC Device Model
  • HMC Analyzer

The Device Model listens on the HMC interface (128-bit) for packets/flits and responds to requests from the Host. The device model VIP is designed to be comply with the HMC Specification v 1.0 and supports all the transaction types mentioned in the specification.

The HMC Analyzer snoops both the TX and RX interfaces of the HMC Device/Host and captures all the packets/flits sent on the bus. It checks the links for compliance with the HMC specification, for example, Link retry, writes and reads. The Analyzer also includes coverage statistics to monitor the number and type of transactions on the HMC interface.

Both these components can be used in tandem or as stand-alone components in the Verification Environment.

Architecture

The HMC Verification IP is developed using a layered architecture as shown in the following figure. This allows both the modules to be highly configurable, coverage driven, and also allows for constrained random generation.

Key features

HMC Device Model features:

  • Fully compliant with the HMC Specification v1.0
  • 128-bit parallel interface for Transmit and Receive of packets/flits.
  • Supports Transaction layer initialization.
  • Supports the full set of commands specified by the HMC specification:
    • Mode Read
    • Mode Write
    • Write16/32/48/64/80/96/112/128
    • Posted Writes Write16/32/48/64/80/96/112/128
    • Read16/32/48/64/80/96/112/128
  • Error detection for CRC/Length/Sequence.
  • Error Injection at the HMC Device Model to test error detection and handling of the Host Controller.
  • Supports Link layer functions like Link Retry, Error Abort Mode.
  • Supports programmable settings for Link Failures and Link Retry.
  • Built-in support for Retry buffers and Link Input buffers.
  • Built-in support for Mode Registers needed to configure the Device Model.
  • Reports Error statistics and Error responses.
  • Generates responses to Reads/Write requests and Mode Read/Write requests, Retry requests.

HMC Analyzer Features:

  • Fully Compliant with HMC specification v1.0.
  • Two 128-bit parallel interfaces to snoop the HMC Transmit and Receive busses.
  • Monitors the HMC interfaces for transactions that take place on them.
  • Transmit and Receive interface monitoring independent of each other.
  • Performs CRC checks on the received packets/flits and flags errors when corrupted packets are detected.
  • Flags errors if packets/flits have malformed headers/tails.
  • Monitors and reports commands
  • Configurable parameters such as Verbosity levels, Threshold timers, retry, error threshold limits and Coverage.
  • Supports three verbosity levels which changes the amount of information printed in the logs.
  • Supports checking of Tag ID, Link ID and Sequence number of packets.
  • Reports errors if Non-posted packet does not receive any response within a time frame or End of Simulation.
  • Transaction and Coverage reports displayed at the End of Simulation.
  • Performance statistics of the Device/Host such as Bandwidth/Speed are displayed.

Block Diagram

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Benefits

  • Seamless integration with OVM/UVM Verification Environments.
  • Configurable components for easy creation of multiple instances of VIP.
  • Configuration options for easy controllability of the VIP.
  • Supports Directed, Random and Constrained Random testing.
  • Built-in Functional coverage to facilitate functional verification analysis.
  • Enables verification at IP-level, SoC and System-level.
  • Documentation with Example codes for testbenches and testcases.

Applications

The HMC VIP can be used to verify any HMC Host Controller which is compliant with the HMC Specification v1.0. The VIP can be used in the functional verification of IPs, SoC designs that incorporate the Hybrid Memory Cube Host Controllers.

  • Device Model VIP Stand-alone configuration:
    • In this configuration, the HMC Device Model alone is used in the verification environment. The Host controller may be an IP or integrated into SoC.
  • HMC Device & Analyzer configuration:
    • In this configuration, both the VIPs are used in tandem, i.e., the Device model as well as the Analyzer. This configuration harnesses the full power of the VIP as it includes complete protocol checking using the analyzer as well as coverage and assertions for transactions. The Analyzer logs will list out each transaction as it happens in the simulation. The analyzer also displays the transaction statistics at the end of the simulation run.

What’s Included?

  • SystemVerilog source code (encrypted).
  • Functional Coverage code which can be modified by users.
  • SystemVerilog testbench.
  • Sanity test cases which covers the functionality.
  • Sample Verification Environment

Specifications

Identity

Part Number
HMC
Vendor
Atria Logic, Inc.
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about HMC Interface IP

What is Hybrid Memory Cube Verification IP?

Hybrid Memory Cube Verification IP is a HMC IP core from Atria Logic, Inc. listed on Semi IP Hub.

How should engineers evaluate this HMC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HMC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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