Vendor: SmartDV Category: HBM

HMC Synthesizable Transactor

HMC Synthesizable Transactor provides a smart way to verify the HMC component of a SOC or a ASIC in Emulator or FPGA platform.

Controller View all specifications

Overview

HMC Synthesizable Transactor provides a smart way to verify the HMC component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's HMC Synthesizable Transactor is fully compliant with standard HMC Specification and provides the following features. Better than Denali Memory Models.

Key features

  • Supports 100% of HMC protocol standard 1.0, 2.0 and 2.1
  • Supports all the HMC commands as per the specs
  • Supports 2,4 and 8 link configuration
  • Supports for half width(8-lanes) and full width(16-lanes)
  • Supports 16, 32, 48, 64, 80, 96, 112, 128 and 256 byte request
  • Supports 12.5 Gb/s, 15 Gb/s, 25 Gb/s, 28 Gb/s, or 30 Gb/s serdes I/O interface
  • Supports packet-based data/command interface
  • Supports poison packets handling
  • Supports scrambler and descrambler
  • Supports training sequence
  • Supports lane reversal and polarity inversion
  • Supports all block size setting
  • Supports flow control
  • Supports link retraining
  • Supports packet retry
  • Checks for following:
    • Check-points include power up,initialization and power off rules
    • State based rules, active command rules
    • Read/Write command rules etc
    • All timing violations
  • Supports various types of error injection support
  • Supports write data mask and data strobe features
  • Supports 4GB/8GB configuration
  • Supports internal ECC data correction
  • Supports error detection (cyclic redundancy check [CRC]) for packets with automatic retry
  • Supports power management supported per link
  • Supports built-in self-test (BIST)
  • Supports JTAG interface (IEEE 1149.1-2001, 1149.6)
  • Supports I2C interface up to 1 MHz
  • Supports SPI master interface
  • Notifies the test bench of significant events such as transactions, warnings,timing and protocol violations

Block Diagram

HMC Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the HMC testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
HMC Transactor
Vendor
SmartDV
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about HBM IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about HBM Interface IP

What is HMC Synthesizable Transactor?

HMC Synthesizable Transactor is a HBM IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this HBM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HBM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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