Vendor: M31 Technology Corp. Category: PLL

M31 Digital PLL IP in 3nm, 5nm, 6nm, 7nm, 12nm, 16nm, 22nm,28nm,40nm

M31 Digital PLL is a core-power only programmable phase-locked loop (PLL) for frequency synthesis.

Contact Provider Request Datasheet

Overview

M31 Digital PLL is a core-power only programmable phase-locked loop (PLL) for frequency synthesis. It supports multiple modes of operation for several application conditions, such as Phase-locked loop (PLL) /Fractional-N phase-locked loop (FNPLL) /Spread spectrum clocking (SSC)/ Oscillator (OSC). M31 Digital PLL has excellent immunity to power supply noise, making it ideally suited for use in noisy ASIC/SoC environments and is available as a single macro for easy integration into any ASIC/SoC.

Key features

  • Pure core voltage design
  • Compact IP size (< 0.013mm²) and low power consumption (1.1mW @ 3GHz)
  • Compatible with commonly used crystal oscillator frequencies
  • Good power noise immunity for period jitter (< ±15%/V)
  • Supports 24-bit fractional accuracy
  • Supports down spread-spectrum clocking (SSC) technology
  • Supports retention OSC operation
  • Embedded lock-detect flag
  • Embedded scan chain for mass production
  • Full deliverables to ease ASIC/SoC integration

Specifications

Identity

Part Number
M31 Digital PLL IP
Vendor
M31 Technology Corp.
Type
Silicon IP

Provider

Contact M31 Technology Corp.

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is M31 Digital PLL IP in 3nm, 5nm, 6nm, 7nm, 12nm, 16nm, 22nm,28nm,40nm?

M31 Digital PLL IP in 3nm, 5nm, 6nm, 7nm, 12nm, 16nm, 22nm,28nm,40nm is a PLL IP core from M31 Technology Corp. listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP