Vendor: T2M GmbH Category: Single-Protocol PHY

LVDS Tx IP, Silicon Proven SMIC 14SF+

The Low-Voltage Differential Signaling Transmitter IP Core provides a very High speed and Low power differential data transfer fo…

SMIC 14nm SF+ In Production View all specifications

Overview

The Low-Voltage Differential Signaling Transmitter IP Core provides a very High speed and Low power differential data transfer for Video interface and advanced Chip to chip interconnection. With a 400Mbps – 2.5Gbps per-lane data rate with up to 16 transmitter and receiver lanes with shared PMU, the LVDS Tx IP Core is a standard for high-speed video data transfer.

Key features

  • Wide-range data rate, up to 1Gbps, the associated clock is DDR clock (1/2 of the data rate, up to 500MHz)
  • 16 channels with a total of 128 bits of parallel data, each channel has a bit width of 8 bits
  • DC coupling mode
  • Multi-channel shared offset
  • Built-in transmitter terminal impedance, no need for off-chip components
  • Support AXI stream bus protocol and data transceiver
  • Built-in self-test mechanism, which can independently complete feature and mass production testing
  • Support link training mode
  • Support Flip-chip package form
  • ESD: HBM/MM/CDM/Latch UP 2000V/200V/500V/100M
  • Silicon Proven in SMIC 14nm SF+

Applications

  • Smart Phone
  • Tablet
  • PC
  • Car navigation
  • Smart TV
  • Digital Still Camera
  • HD Camera

What’s Included?

  • Compliant with IEEE 1596.3 Standard
  • Supports Data Rate upto 1.6 Gbps
  • Supports reduced swing mode
  • X7 Multiplier PLL for serial clock generation
  • Configurable analog characteristics
  • PLL loop filter
  • PLL VCO gain
  • Differential voltage Common-mode voltage
  • Pre-emphasis strength

Silicon Options

Foundry Node Process Maturity
SMIC 14nm SF+ In Production

Specifications

Identity

Part Number
LVDS Tx IP in 14SF+
Vendor
T2M GmbH
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Germany

Learn more about Single-Protocol PHY IP core

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UFS Goes Mainstream

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Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is LVDS Tx IP, Silicon Proven SMIC 14SF+?

LVDS Tx IP, Silicon Proven SMIC 14SF+ is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for smic In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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