Vendor: Xilinx, Inc. Category: Debug Trace

LogiCore AXI Traffic Generator

Included at no additional charge with Vivado Design and System edition of software.

Overview

Included at no additional charge with Vivado Design and System edition of software.



Xilinx provides AXI Traffic Generator IP which as AXI4 Master can generate AXI4 traffic (AXI4 and AXI4-Stream) for various modules/interconnect connected in system

The Xilinx LogiCORE™ IP Advanced eXtensible Interface (AXI) Traffic Generator is a core that stresses the AXI4 and AXI4-Stream interconnect and other AXI4 peripherals in the system. It generates a wide variety of AXI4 transactions based on the core programming

Key features

  • AXI4 interface for register access and data transfers
  • Supports multi-mode operation (AXI4-Master, AXI4-Slave, AXI4-Stream Master)
  • Flexible data width capability (32/64-bit) on Slave, (32/64/128/256/512-bit) on Master AXI4 interface and (8/16/32/64/128/256/512/1,024-bit) on Master AXI4-Stream interface
  • Supports AXI4-Lite Master interface for system initialization in processor-less system
  • Interrupt pin indicating core completed generation of traffic
  • Error interrupt pin indicating error occurred during core operation. Error registers can be read to understand the error occurred
  • Initialization support to internal RAM (CMDRAM, PARAMRAM, and MSTRAM) allows user to initialize the contents of all RAMs for a desired traffic profile
  • External global start/stop to synchronize all AXI Traffic Generators in system and to enable AXI Traffic Generator without processor intervention
  • Supports High level traffic generation for different traffic profiles such as Ethernet, Video, PCIe
  • Supports infinite looping over its read and write queues to generate traffic for long running test cases (e.g. when running in parallel with SW)

Specifications

Identity

Part Number
LogiCore AXI Traffic Generator
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA

Learn more about Debug Trace IP core

Designing FPGA Based Reliable Systems Using Virtex-5 System Monitor

The fast track development and 24x7 operations have put tremendous pressure on the servers, networking systems and communication equipments. It has become necessary that these systems should operate reliably irrespective of the change in external operating environment like the temperature, humidity, and power fluctuations or, on chip conditions like on-chip temperature, internal voltage levels etc. Measuring the reliability of these physical systems is must for every operational unit.

How to maximize FPGA performance

The more that can be done upfront with good coding styles, timing constraints definition, and resource planning, the easier it will be for the downstream tools to achieve timing requirements.

Frequently asked questions about Debug Trace IP

What is LogiCore AXI Traffic Generator?

LogiCore AXI Traffic Generator is a Debug Trace IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Debug Trace?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Debug Trace IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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