High Speed Ethernet Gen-2 Quad 100G PCS IP
The 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a set of features that enab…
- Single-Protocol PHY
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
High Speed Ethernet Gen-2 Quad 100G PCS IP
The 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a set of features that enab…
High Speed Ethernet 4/2/1-Lane 100G PCS
The 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a set of features that enab…
High Speed Ethernet 2/4/8-Lane 200G/400G PCS
The Ethernet 400G and 200G Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802.3bs standard and provides a set of fe…
High Speed Ether 2/4/8-Lane 200G/400G/800G PCS
The 800G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the 400G IEEE 802.3bs standard, provides a set of features en…
High Speed Ethernet 200G/400G/800G MAC
The 100G/200G/400G/800G Ethernet MAC IP implements the full MAC layer and reconciliation sublayer compliant with the IEEE 802.3 s…
High Speed Ethernet 200G/400G MAC
The 100G/200G/400G/800G Ethernet MAC IP implements the full MAC layer and reconciliation sublayer compliant with the IEEE 802.3 s…
High Speed Ethernet 100G MAC IP
The 100G/200G/400G/800G Ethernet MAC IP implements the full MAC layer and reconciliation sublayer compliant with the IEEE 802.3 s…
112G Ethernet PHY, TSMC N5 x4, North/South (vertical) poly orientation
The 112G Ethernet PHY IP, an integral part of the 400GbE/800GbE Ethernet solution enables long reach (LR), medium reach (MR), ver…
1-port Receiver/Transmitter HDCP 2.3 on DisplayPort 1.4/2.0 ESM (generation 3)
The HDCP 2.3 Embedded Security Modules (ESMs) on DisplayPort are autonomous modules that provide designers with a and robust tran…
USB-C 3.1/DisplayPort 1.4 IP Subsystem Solution
Synopsys has pre-integrated USB-C 3.1/DisplayPort 1.4 IP into a single subsystem solution to save customers more than two enginee…
SuperSpeed USB 3.1 Host Controller
The vendor provides designers with silicon-proven, configurable USB 3.1 Controllers.
SuperSpeed USB 3.1 DRD Controller
The vendor provides designers with silicon-proven, configurable USB 3.1 Controllers.
SuperSpeed USB 3.1 Device Controller
The vendor provides designers with silicon-proven, configurable USB 3.1 Controllers.
DisplayPort 1.4 TX PHY, TSMC N5, North/South Poly Orientation
The USB-C 3.1/DisplayPort 1.4 IP solution consists of USB-C 3.1/DisplayPort 1.4 PHYs, USB-C 3.1/DisplayPort 1.4 controllers (Devi…
The High-Bandwidth Interconnect PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for…
Die-to-Die, AIB 2.0 PHY Ported to Intel 16, North/South (vertical) poly orientation
The High-Bandwidth Interconnect PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for…
The XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in mult…
D2D Controller addon for D2D SR112G PHY with CXS interface
The Die-to-Die Controller IP, optimized for latency, bandwidth, power, and area, enables efficient inter-die connectivity in serv…
UCIe-S PHY for Standard Package (x16) in TSMC N5, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-A PHY for Advanced Package (x64) in TSMC N5, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …