Vendor: FortifyIQ, Inc. Category: Post Quantum

Hybrid Classical and Post-Quantum Cryptography

Hybrid Classical and Post-Quantum Cryptography IP Core for Future-Proof Security FortifyIQ’s Hybrid Cryptography IP core combines…

Overview

Hybrid Classical and Post-Quantum Cryptography IP Core for Future-Proof Security

FortifyIQ’s Hybrid Cryptography IP core combines traditional asymmetric algorithms—such as RSA and ECC—with post-quantum standards including ML-KEM (Kyber) and ML-DSA (Dilithium)—in a single, efficient hardware module. Designed for applications requiring smooth migration to quantum-safe cryptography, it enables hybrid key exchange and digital signature schemes that meet both current and future security standards. Optimized for balanced power, area, and performance, the IP supports secure SoC integration with protections against side-channel and fault injection attacks, making it suitable for FIPS 140-3 and Common Criteria certification. Ideal for secure boot, firmware authentication, and long-lifecycle systems requiring cryptographic agility.

External Dependencies

Requires an external cryptographically secure random number generator (CSPRNG)

Key features

  • Efficient Performance
  • SCA/FIA Protections
  • Patented High-Performance Modulo Multiplication
  • Flexible Interfaces
  • RAM/ROM Firmware Support
  • Security Certification Readiness

Applications

  • IoT Devices
  • Automotive Systems
  • Embedded and Industrial Control
  • Authentication Tokens
  • Payment Systems
  • Secure Communications
  • Network Devices

What’s Included?

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Firmware code
  • Software library
  • Security documentation

Specifications

Identity

Part Number
FIQ-PQC04B
Vendor
FortifyIQ, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Post Quantum IP core

How to design secure SoCs Part IV: Runtime Integrity Protection

In previous articles, we gave an overview about secure SoC architectures (Part I), about the importance of key management (Part II) and secure boot (Part III) - the first line of defense. Part IV of the series focuses on runtime integrity protection, a paramount, ensuring the application remains secure even during active operation.

How to design secure SoCs Part IV: Runtime Integrity Protection

SoC designers are increasingly challenged to integrate robust security measures into their designs. Modern connected devices, such as automotive Electronic Control Units (ECUs), Internet of Things (IoT) nodes, and industrial control systems, face increasing susceptibility to cyberattacks. This escalating threat landscape underscores the critical importance of mandatory security requirements.

Nine Compelling Reasons Why Menta eFPGA Is Essential for Achieving True Crypto Agility in Your ASIC or SoC

Today’s world is already overly complicated to provide robust product security, with extremely motivated hackers creating novel threats exposing new vulnerabilities every day. But considering tomorrow’s world with the looming threat of quantum computing, expanding AI possibilities and rapidly evolving regional regulations and export control risk with severe financial penalties, this is a daunting challenge.

Providing protection against EMFI attacks

This Agile Analog blog post is focused on describing the dangers of Electromagnetic Fault Injection (EMFI) attacks and outlining the importance of EMFI sensors that are designed to provide protection.

Deploying StrongSwan on an Embedded FPGA Platform, IPsec/IKEv2 on Arty Z7 with PetaLinux and PQC

The objective of this article is to present and analyze a concrete IPsec/IKEv2 deployment on an FPGA-based embedded Linux system. Using an Arty Z7 FPGA platform with PetaLinux and StrongSwan, the focus is on system-level integration rather than protocol theory: how the IPsec stack is built and deployed, how classical and post-quantum key exchange are integrated without modifying standardized protocols, and what architectural trade-offs arise when moving cryptographic operations into programmable logic.

Frequently asked questions about Post-Quantum Cryptography IP cores

What is Hybrid Classical and Post-Quantum Cryptography?

Hybrid Classical and Post-Quantum Cryptography is a Post Quantum IP core from FortifyIQ, Inc. listed on Semi IP Hub.

How should engineers evaluate this Post Quantum?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Post Quantum IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP