Vendor: SmartDV Technologies Category: HBM

GHBM Memory Model

GHBM Memory Model provides an smart way to verify the GHBM component of a SOC or a ASIC.

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Overview

GHBM Memory Model provides an smart way to verify the GHBM component of a SOC or a ASIC. The SmartDV's GHBM memory model is fully compliant with standard GHBM Specification and provides the following features. Better than Denali Memory Models.

GHBM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

GHBM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports GHBM memory devices from all leading vendors.
  • Supports 100% of GHBM protocol standard JEDEC.
  • Supports all the GHBM commands as per the specs.
  • Supports programmable clock frequency of operation.
  • Supports all types of timing and protocol violation detection.
  • Supports burst length of 4 and 8.
  • Supports Programmable READ/WRITE Latency timings.
  • Supports Bank grouping.
  • Supports 8 and 16 banks per channel.
  • Supports up to 8 channels per stack.
  • Checks for following
    • Check-points include power on, Initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Commands rules etc.
    • All timing violations.
  • Supports callbacks for user to get command data on bus.
  • Supports All Mode registers programming.
  • Supports DBIac write and read.
  • Supports Legacy Mode and Pseudo Channel Mode Operation (64 DQ width for Pseudo Channel Mode).
  • Supports Self-Refresh Modes.
  • Supports channel density of 1 GB to 32 GB.
  • Supports 128 DQ width + Optional ECC pin support/channel.
  • Supports ECC.
  • Supports write data mask and data strobe features.
  • Supports for power down features.
  • Supports for input clock stop and frequency change.
  • Supports for target row refresh mode.
  • Supports for temperature compensated refresh reporting.
  • Supports for IEEE standard 1500.
  • Bus-accurate timing for min, max and typical values.
  • Constantly monitors GHBM behavior during simulation.
  • Protocol Checker fully compliant with GHBM Specification.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Block Diagram

GHBM Memory Model block diagram

Benefits

  • Faster testbench development and more complete verification of GHBM designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the GHBM testcases.
  • Complete UVM/OVM sequence library for GHBM controller.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
GHBM Memory Model
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

Learn more about HBM IP core

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Frequently asked questions about HBM Interface IP

What is GHBM Memory Model?

GHBM Memory Model is a HBM IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this HBM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HBM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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