Vendor: True Circuits, Inc. Category: PLL

GF L65G 65nm Clock Generator PLL - 180MHz-900MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.

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GlobalFoundries 65nm G View all specifications

Overview

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock input, a 1-4096 divider in the internal feedback path, and a 1-8 divider at the output. The outputs are 50% duty cycle for all output divider values.

Key features

  • Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
  • Delivers optimal jitter performance over all multiplication settings.
  • Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
  • Ideal for system clock generation, SerDes and video clock applications.

What’s Included?

  • GDSII (100% DRC and LVS clean)
  • LVS Spice netlist
  • Verilog model
  • Synopsys synthesis model
  • LEF for clock generator PLL
  • User Guidelines including:
    • integration guidelines,
    • layout guidelines,
    • testability guidelines,
    • packaging guidelines,
    • board-level guidelines

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 65nm G —

Specifications

Identity

Part Number
TCI-CL65G-CGMPLL
Vendor
True Circuits, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact True Circuits, Inc.

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Frequently asked questions about PLL IP cores

What is GF L65G 65nm Clock Generator PLL - 180MHz-900MHz?

GF L65G 65nm Clock Generator PLL - 180MHz-900MHz is a PLL IP core from True Circuits, Inc. listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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