Vendor: SmartDV Category: GPIO

GCI Synthesizable Transactor

The GCI Synthesizable Transactor is compliant with V1.0 specifications and verifies GCI interfaces.

Overview

The GCI Synthesizable Transactor is compliant with V1.0 specifications and verifies GCI interfaces. GCI is build on top of it to make it robust. GCI Synthesizable Transactor provides a smart way to verify the GCI component of a SOC or a ASIC in Emulator or FPGA platform. GCI Synthesizable Transactor is developed by experts in networking, who have developed networking products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a networking product.

Key features

  • Compliant to GCI protocol specification v1.0
  • Supports fixed-sized frames
  • Supports configurable number of serial lanes as per the specification
  • Supports 10 bit per lane serdes interface
  • Supports training sequence as per spec
  • Reset the data link layer
  • Supports configurable Tx and Rx long term CRC function per lane
  • Supports CID and Idle/Pause frames
  • Supports Scrambler as per spec
  • Supports lane reordering as per spec
  • Supports breaking of frames into sub-frames
  • Supports replay and error recovery
  • Supports polarity inversion
  • Supports Per lane skew insertion to test lane alignment
  • Supports Addressable registers
  • Supports very flexible way to test sync and alignment for state machines at startup
  • Recovers clock from input serial data stream
  • Supports all types of error insertion and detection
    • CRC errors
    • Pause frame errors
    • Bad scrambler state
    • Lane alignment failure
    • Disparity errors
    • Invalid code group insertion
    • Invalid /K/ characters insertion
    • Lane Skew insertion

Block Diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the GCI testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
GCI Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: India

Learn more about GPIO IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about GPIO IP cores

What is GCI Synthesizable Transactor?

GCI Synthesizable Transactor is a GPIO IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this GPIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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