Vendor: SmartDV Technologies Category: GPIO

GCI Verification IP

The GCI Verification IP is compliant with 1.3 specifications and verifies GCI interfaces of designs GCI Interface.

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Verification IP View all specifications

Overview

The GCI Verification IP is compliant with 1.3 specifications and verifies GCI interfaces of designs GCI Interface. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. GCI Verification IP is developed by experts in networking, who have developed networking products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a networking product.

GCI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

GCI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Follows GCI specification as defined in GCI specification v1.3.
  • Recovers clock from input serial data stream
  • Supports fixed-sized frames
  • Supports 10 bit per lane serdes interface
  • Supports configurable number of lanes as per the specification
  • Supports training sequence as per spec
  • Reset the data link layer
  • Supports configurable Tx and Rx long term CRC function per lane
  • Per lane skew insertion to test lane alignment.
  • Supports very flexible way to test sync and alignment for state machines at startup.
  • Supports CID and Idle/Pause frames.
  • Supports Scrambler as per spec
  • Supports lane reordering as per spec
  • Supports breaking of frames into sub-frames.
  • Supports replay and error recovery
  • Supports polarity inversion
  • Addressable registers
  • Following error injection is supported
    • CRC errors
    • Framing errors
    • Pause frame errors
    • Bad scrambler state
    • Lane alignment failure
    • Disparity errors
    • Invalid code group insertion
    • Invalid /K/ characters insertion
    • Lane Skew insertion
  • Rich set of configuration parameters to control GCI functionality
  • Callbacks in TX, RX and monitor for user processing of data
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Complete functional coverage for both normal and error cases.
  • GCI verification IP comes with complete testsuite to test every feature of GCI specifications.
  • Supports CID violation
  • Supports CRC-12 for pairs of frame
  • Supports Error Recovery modes
    • Host Error Recovery
    • Automatic Error Recovery

Block Diagram

GCI VIP block diagram

Benefits

  • Faster testbench development and more complete verification of GCI designs
  • Easy to use command interface simplifies testbench control and configuration of GCI TX and RX
  • Simplifies results analysis
  • Runs in every major simulation environment

What’s Included?

  • Complete regression suite containing all the GCI testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
GCI VIP
Vendor
SmartDV Technologies
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

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Frequently asked questions about GPIO IP cores

What is GCI Verification IP?

GCI Verification IP is a GPIO IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this GPIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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