Overview
FREQDET28HPC is an IP for detection of input frequency and provides digital output as well as analog output to be used as indicator of the input frequency.
Basic principal of operation is frequency to voltage converter and converted analog output voltage is dependent on the process corner of the poly resistance and mom capacitor. IP can self-calibrate when predefined input frequency is applied at the calibration input. When a predefined calibration input is applied at the FCAL input pin and CAL=1, IP enters into self-calibration mode to trim the internal RINT, CREF and resulting calibration codes are provided to be stored in static memory of e-fuse. Post calibration it produces the output voltage and digitally converted 4b output to indicate the output frequency of the applied input which is proportional to the applied input frequency. IP includes complete reference generation, trimming circuits, digitizer and calibration engine. During normal operation mode when CAL=0, to trim the internal RC, Digital data DTRIM has to be applied from stored memory during calibration phase.
Learn more about PLL IP core
How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.
Jian Yang, Sween Kang (Synopsys)
This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.
This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.
In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.
This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.
