Dual Port SRAM Compiler IP, UMC 28nm HLP process
Faraday Technology
•
HQ:
Taiwan
UMC 28nm HLP/ Low-K Dual Port SRAM compiler.
- UMC
- 28nm
- HLP
Compare 2,955 UMC IP Cores from 31 vendors
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Dual Port SRAM Compiler IP, UMC 0.18um G2 process
Faraday Technology• HQ: TaiwanUMC 0.18um GII Logic process synchronous high density Dual Port (2RW) SRAM memory compiler.
- UMC
- 180nm
- G
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Dual Port SRAM Compiler IP, UMC 0.18um G2 process
Faraday Technology• HQ: TaiwanUMC 0.18um GII Logic process synchronous high density Dual Port (2RW) SRAM memory compiler.
- UMC
- 180nm
- G
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Dual Port SRAM Compiler IP, UMC 0.13um LL process
Faraday Technology• HQ: TaiwanUMC 0.13um LL Logic/FSG process high density synchronous high density Dual Port (2RW) SRAM memory compiler.
- UMC
- 130nm
- LL
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Dual Port SRAM Compiler IP, UMC 0.13um HS/FSG process
Faraday Technology• HQ: TaiwanUMC 0.13um HS/FSG Logic process Synchronous high density Dual Port SRAM memory compiler with input wrapper Mux.
- UMC
- 130nm
- HS
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Dual Port SRAM Compiler IP, UMC 0.11um SP process
Faraday Technology• HQ: TaiwanUMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous High-density Dual Port SRAM memory compiler.
- UMC
- 110nm
- SP
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Dual Port SRAM Compiler IP, UMC 0.11um LL process
Faraday Technology• HQ: TaiwanUMC 0.11um low leakage Logic process synchronous high density Dual Port SRAM memory compiler.
- UMC
- 110nm
- LL
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Dual Port SRAM Compiler IP, UMC 0.11um eFlash/LL process
Faraday Technology• HQ: TaiwanUMC 0.11um eFlash LL process Dual Port SRAM compiler.
- UMC
- 110nm
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Dual Port SRAM Compiler IP, UMC 0.11um eFlash/HS process
Faraday Technology• HQ: TaiwanUMC 0.11um eFlash HS process, Dual Port SRAM compiler.
- UMC
- 110nm
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Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm eHV process
Faraday Technology• HQ: TaiwanUMC 55nm eHV process, Dual Port SRAM compiler with row redundancy option.
- UMC
- 55nm
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Dual Port SRAM Compiler IP, High density, (2RW), UMC 0.13um HS/FSG process
Faraday Technology• HQ: TaiwanUMC 0.13um HS/FSG Logic process high density synchronous Dual Port (2RW) SRAM memory compiler.
- UMC
- 130nm
- HS
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DLL (All Digital) IP, Input: 5MHz - 70MHz, Output: 5MHz - 70MHz, UMC 40nm LP process
Faraday Technology• HQ: TaiwanAn ADDLL operate at 5MHz~70MHz.Output produce a rising/falling edge delay tuning clock.UMC 40nm LP/RVT Logic process.
- UMC
- 40nm
- LP
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DLL (All Digital) IP, Input: 360MHz - 720MHz, Output: 360MHz - 720MHz, UMC 40nm LP process
Faraday Technology• HQ: TaiwanInput 360M-720MHz, output 360M-720MHz, DLL, Output 0-180 degree Phase adjustment range.
- UMC
- 40nm
- LP
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DLL (All Digital) IP, Input: 300MHz - 600MHz, Input: 300MHz - 600MHz, UMC 40nm LP process
Faraday Technology• HQ: TaiwanAn ADDLL operate at 300MHz~600MHz.Output 0-180 degree Phase adjustment range.Delay adjustment resolution
- UMC
- 40nm
- LP
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DDR DLL IP, Input: 66MHz - 200MHz, Output: 66MHz - 200MHz, UMC 90nm SP process
Faraday Technology• HQ: TaiwanInput 66M-200MHz, output 66M-200MHz, DDR DLL, UMC 90nm SP/RVT Low-K Logic process.
- UMC
- 90nm
- SP
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DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz -200MHz, UMC 0.18um G2 process
Faraday Technology• HQ: TaiwanInput 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.18um GII Logic process.
- UMC
- 180nm
- G
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DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.13um HS/FSG process
Faraday Technology• HQ: TaiwanInput 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.13um HS/FSG Logic process.
- UMC
- 130nm
- HS
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DDR DLL IP, Input: 100MHz - 150MHz, Output: 100MHz - 150MHz, UMC 0.18um G2 process
Faraday Technology• HQ: TaiwanInput 100M-150MHz, output 100M-150MHz, DDR DLL, UMC 0.18um GII Logic process.
- UMC
- 180nm
- G
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Faraday Technology• HQ: Taiwan
PWM controller with soft start function for DC to DC boost converter, UMC 0.13um HS/FSG Logic process.
- UMC
- 130nm
- HS
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DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.18um G2 process
Faraday Technology• HQ: TaiwanPulse width modulation, boosting voltage from 3.3V to 5V, 50mA driving capability, Ivcca=140uA @ Idrive=0.
- UMC
- 180nm
- G