The Platform Based SOC Design that Utilizes Structured ASIC Technology
The Platform Based SOC Design that Utilizes Structured ASIC Technology
Vendor:
Faraday Technology
Category:
DLL
DLL (All Digital) IP, Input: 300MHz - 600MHz, Input: 300MHz - 600MHz, UMC 40nm LP process
An ADDLL operate at 300MHz~600MHz.Output 0-180 degree Phase adjustment range.Delay adjustment resolution
Overview
An ADDLL operate at 300MHz~600MHz.Output 0-180 degree Phase adjustment range.Delay adjustment resolution <= 1% of reference clockUMC 40nm LP/RVT Logic process.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 40nm | LP | — |
Specifications
Identity
Part Number
FXADDLL330HH0L
Vendor
Faraday Technology
Type
Silicon IP
Provider
HQ:
Taiwan
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Frequently asked questions about DLL IP cores
What is DLL (All Digital) IP, Input: 300MHz - 600MHz, Input: 300MHz - 600MHz, UMC 40nm LP process?
DLL (All Digital) IP, Input: 300MHz - 600MHz, Input: 300MHz - 600MHz, UMC 40nm LP process is a DLL IP core from Faraday Technology listed on Semi IP Hub. It is listed with support for umc.
How should engineers evaluate this DLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.