General Purpose IO IP, UMC 0.25um Logic process
UMC 0.25um Logic process true 3.3V standard IO Cell Library.
- UMC
- 250nm
General Purpose IO IP, UMC 0.25um Logic process
UMC 0.25um Logic process true 3.3V standard IO Cell Library.
General Purpose IO IP, UMC 0.25um Logic process
UMC 0.25um Logic process true 2.5V standard IO Cell Library.
General Purpose IO IP, 5V tolerance, UMC 0.25um Logic process
UMC 0.25um Logic process 5V tolerance standard IO Cell Library.
General Purpose IO IP, UMC 0.25um Logic process
UMC 0.25um Logic process true 3.3V standard IO Cell Library.
General Purpose IO IP, UMC 0.25um Logic process
UMC 0.25um Logic process true 2.5V standard IO Cell Library.
General Purpose IO IP, 5V tolerance, UMC 0.25um Logic process
UMC 0.25um Logic process 5V tolerance standard IO Cell Library.
General Purpose IO IP, 3.3V tolerance, UMC 0.25um Logic process
UMC 0.25um Logic process 3.3V tolerance standard IO Cell Library.
General Purpose IO IP, UMC 0.18um LL process
UMC 0.18um LL Logic process true 3.3V standard IO Cell Library.
General Purpose IO IP, 5V input tolerance, UMC 0.18um LL process
UMC 0.18um LL Logic process 5V tolerance standard IO Cell Library.
General Purpose IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process true 3.3V standard IO Cell Library.
General Purpose IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process true 1.8V standard IO Cell Library.
General Purpose IO IP, 5V input tolerance, UMC 0.18um G2 process
UMC 0.18um GII Logic process 5V tolerance standard IO Cell Library.
General Purpose IO IP, UMC 0.13um process
UMC 0.13um ture 3.3V Generic IO IP.
General Purpose IO IP, 5V tolerance, UMC 0.13um process
UMC 0.13um 5V tolerance gengric IO.
General Purpose IO IP, SD3.0 I/O, Support built-in Pull-Up / Pull-Down , UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process 1.8V BOAC EMMC IO Cell Library (with customized PU/PD function).
Dual Port SRAM Compiler IP, UMC 90nm SP process
UMC 90nm SP/RVT/ Low-K process synchronous Dual Port SRAM compiler.
Dual Port SRAM Compiler IP, UMC 55nm LP process
UMC 55nm LP/ Low-K process with row Redundancy Dual Port SRAM compiler.
Dual Port SRAM Compiler IP, UMC 55nm eHV process
UMC 55nm eHV process, Dual Port SRAM compiler.
Dual Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP Logic process, Dual Port SRAM compiler with R1.
Dual Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP Logic process, Dual Port SRAM compiler with LVT.