Standard Cell PowerSlash(TM) Library IP, HVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic process 9-Track POWERSLASH Core Core Cell Library.
- UMC
- 28nm
- HLP
Standard Cell PowerSlash(TM) Library IP, HVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic process 9-Track POWERSLASH Core Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/HVT Logic and Mixed-Mode process 7-Track POWERSLASH Kit Cell Library C35.
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library with LPLUS (C38).
Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process 12-Track high performance Cell Library.
Standard Cell (Ultra High Speed) Library IP, LVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Low-K Logic process 12-Track high performance Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Low-K Logic process 12-Track Standard Cell Library.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process high density Core Cell Library.
Standard Cell (Generic) Library IP, 10-track, RVT, UMC 90nm SP process
UMC 90nm SP Logic Low-K process standard Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.25um process
UMC 0.25um Logic process standard Cell Library.
Standard Cell (Generic) Library IP, UMC 0.25um process
UMC 0.25um Logic process standard Cell Library.
Standard Cell (Generic) Library IP, UMC 0.25um process
UMC 0.25um Logic process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.25um process
UMC 0.25um Logic process shrink (0.22um) mask programmable cell array with body A Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.18um MS process
UMC 0.18um Mixed-Mode / RFCMOS process standard Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.18um LL process
UMC 0.18um LL Logic process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.18um LL process
UMC 0.18um LL Logic process standard Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process standard Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.15um SP process
UMC 0.15um SP Logic process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um SP process
UMC 0.13um Logic high speed(FSG) process, Metal programmable(M3/M4/M5) cell array Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um SP process
UMC 0.13um SP/FSG Logic process mask programmable cell array with body E Core Cell Library.