Standard Cell (Generic) Library IP, LVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/LVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library (C40).
- UMC
- 28nm
- HPC
Standard Cell (Generic) Library IP, LVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/LVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library (C40).
Standard Cell (Generic) Library IP, LVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/LVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library (C35).
Standard Cell (Generic) Library IP, LVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/LVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library (C30).
Standard Cell (Generic) Library IP, LVT, 12 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic process 12-Track Standard Generic Core Cell Library (C30).
Standard Cell (Generic) Library IP, 10-track, HVT, UMC 90nm SP process
UMC 90nm Low-K SP/HVT Standard Core Cell Library.
Standard Cell (Generic) Library IP, HVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic process 9-Track Generic Core Cell Library (C38).
Standard Cell (Generic) Library IP, HVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic process 9-Track Generic Core Cell Library.
Standard Cell (Generic) Library IP, HVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library C40.
Standard Cell (Generic) Library IP, HVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library C35.
Standard Cell (Generic) Library IP, HVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library C30.
Standard Cell (Generic) Library IP, HVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library with LPLUS (C38).
Standard Cell (Generic) Library IP, HVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Cell Library with LMINUS (C30 HVT).
Standard Cell (ECO) Library IP, RVT, UMC 65nm SP process
metal-1 start Gate Array ECO Library for UMC 65nm SP/RVT(FSE0A_D).
Standard Cell (ECO) Library IP, RVT, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process ECO_M1 Core Cell Library.
Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track ECO_M1 Cell Library (C35).
Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track ECO Cell Library with LPLUS (C38).
Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track ECO Cell Library with LMINUS (C30 RVT).
Standard Cell (ECO) Library IP, LVT, UMC 40nm LP process
UMC 40nm LP/LVT Low-K Logic process ECO_M1 Core Cell Library.
Standard Cell (ECO) Library IP, LVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic process 9-Track Standard Generic ECO Cell Library (C35).
Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/LVT Logic and Mixed-Mode process 7-Track ECO_M1 Cell Library (C35).