UMC IP Cores

USB 3.0 PHY, UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT process.

• UMC
• 40nm
• LP

Crystal-less USB 3.0 PHY, UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT process.

• UMC
• 40nm
• LP

USB2.0 OTG PHY, UMC 55nm eFlash process.

• USB 2.0
• UMC
• 55nm

OTG USB2.0 UMC 40 nm LP/RVT process.

• USB 2.0
• UMC
• 40nm
• LP

USB 2.0 host On-The-Go PHY, UMC 0.25um Logic process.

• USB 2.0
• UMC
• 250nm

USB 2.0 On-The-Go PHY, UMC 0.18um GII Logic RVT/FSG process.

• USB 2.0
• UMC
• 180nm
• G

USB 2.0 On-The-Go PHY, UMC 0.13um HS/FSG Logic process.

• USB 2.0
• UMC
• 130nm
• HS

USB2.0 Analog PHY, UMC 0.18um GII Logic RVT/FSG process.

• USB 2.0
• UMC
• 180nm
• G

USB2.0 PHY (Pure device mode), UMC 0.18um GII Logic RVT/FSG process.

• USB 2.0
• UMC
• 180nm
• G

USB 2.0 PHY, UMC 0.13um LL Logic process.

• USB 2.0
• UMC
• 130nm
• LL

USB 2.0 PHY, crystal-less option, UMC 40nm LP/RVT process.

• USB 2.0
• UMC
• 40nm
• LP

0.13um OTG PHY, UMC 0.13um HS/FSG process.

• UCIe 1.1
• UMC
• 130nm
• HS

USB 1.1 transceiver, UMC 0.18um GII Logic process.

• UCIe 1.1
• UMC
• 180nm
• G

USB 1.1 PHY, UMC 0.18um GII Logic process 1.8/3.3V.

• UCIe 1.1
• UMC
• 180nm
• G

UMC 90nm SP Logic Low-K process synchronous Two Port (1R1W) Register File SRAM memory compiler.

• UMC
• 90nm
• SP

UMC 55nm LP/ Low-K process PG Two Port Register File compiler.

• UMC
• 55nm
• LP

UMC 40nm LP Two Port Register File with Sleep/Retention/Nap mode feature.

• UMC
• 40nm
• LP

UMC 40nm LP/LVT process, Two Port Register File with LVT.

• UMC
• 40nm
• LP

UMC 40nm LP/ Low-K process, Two Port Register File memory compiler.

• UMC
• 40nm
• LP

UMC 28nm HLP peripheral LVT Two Port Register File memory compiler.

• UMC
• 28nm
• HLP