UMC IP Cores

28nm HPM SP-SRAM with Row and 2 Column Repair

• UMC
• 28nm
• HPM

28nm HPM SP-SRAM with row and 1 column repair

• UMC
• 28nm
• HPM

UMC 28nm HPM process synchronous LVT preiphery high density single port SRAM memory compiler with Row and 2 Column Repair

• UMC
• 28nm
• HPM

28nm HPM SP-SRAM with peri LVT & row & 1 column repair

• UMC
• 28nm
• HPM

28nm HPM SP-SRAM with peri LVT & 2 column repair

• UMC
• 28nm
• HPM

28nm HPM SP-SRAM with peri-LVT 1 column repair

• UMC
• 28nm
• HPM

28nm HPM SP-SRAM with 2 column redundancy

• UMC
• 28nm
• HPM

28nm HPM SP-SRAM with 1 column redundancy

• UMC
• 28nm
• HPM

UMC 28nm HPC process standard synchronous LVT periphery high density single port low power SRAM memory compiler with row redundan…

• UMC
• 28nm
• HPC

UMC 28nm HPC process standard synchronous HVT periphery high density single port low power SRAM memory compiler with row redundan…

• UMC
• 28nm
• HPC

UMC 28nm HPC Logic Process Ultra High Density Single-Port SRAM Memory Compiler

• UMC
• 28nm
• HPC

UMC 55nm ULP-SST process PG One Port Register File for periphery HVT

• UMC
• 55nm
• ULP

UMC 0.11um HS/AL Logic Process High Density Version MPCA core cell library with mini programming layer from V1 to M4

• UMC
• 110nm
• HS

UMC 0.11um HS/ALE Logic Process MPCA Cell Library With minimum Via1/M2/Via2/M3/Via3/M4 programming

• UMC
• 110nm
• HS
• Pre-Silicon

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)

• UMC
• 28nm
• HPC

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)

• UMC
• 28nm
• HPC

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)

• UMC
• 28nm
• HPC

UMC 40nm LP/RVT Logic Process SYNS-like 9T POWERSLASH Cell Library

• UMC
• 40nm
• LP

UMC 40nm LP/LVT Logic Process SYNS-like 9T POWERSLASH Cell Library

• UMC
• 40nm
• LP

UMC 40nm LP/HVT Logic Process SYNS-like 9T POWERSLASH Cell Library

• UMC
• 40nm
• LP