The Platform Based SOC Design that Utilizes Structured ASIC Technology
The Platform Based SOC Design that Utilizes Structured ASIC Technology
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35)
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 28nm | HPC | Pre-Silicon |
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35) is a Standard Cell Libraries IP core from Faraday Technology listed on Semi IP Hub. It is listed with support for umc Pre-Silicon.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Standard Cell Libraries IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.