UMC IP Cores

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

• Controller + PHY + 1
• UMC
• 55nm
• LP

Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, …

• UMC
• 40nm
• LP

12 bit 1MSPS R-2R DAC; UMC 55nm eFlash process

• 12 Bit
• UMC
• 55nm

12bits 1MHz Voltage output R-2R D/A Converter; UMC 55nm SP-RVT process

• 12 Bit
• UMC
• 55nm
• SP

10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm ULP process

• 10 Bit
• UMC
• 55nm
• ULP

10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm eFlash (SST) process

• 10 Bit
• UMC
• 55nm
• ULP

10bit 250MSPS Current-steering Video D/A Converter; UMC 0.11um HS/FSG Logic Process

• 10 Bit
• UMC
• 110nm
• HS

10bit 150MSPS 3-ch Video DAC,UMC 28nm HPC process

• 10 Bit
• UMC
• 28nm
• HPC

CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process

• UMC
• 28nm
• HPC

MIPI Transmitter CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process

• MIPI D-PHY
• UMC
• 28nm
• HPC

MIPI Receiver CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process

• MIPI D-PHY
• UMC
• 28nm
• HPC

Power input 1.8v, VBG=0.75V Band-gap, UMC 28nm HPC Logic process

• UMC
• 28nm
• HPC

Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC+ Process

• UMC
• 28nm
• HPC+

Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC Process

• UMC
• 28nm

Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process

• UMC
• 65nm
• LL

Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm LP/RVT Logic Process

• UMC
• 55nm
• LP

Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process

• UMC
• 55nm

Input 2.5V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process

• UMC
• 40nm
• LP

Power input 3.3V, VBG=1.204V Band-gap, UMC 55nm eFlash process

• UMC
• 55nm

FXAFE030HH0L is an Analog Front End IP for image processing applications.

• UMC
• 40nm