Overview
FXAFE010HF0A is an Analog Front End IP for CMOS image processing applications. FXAFE010HF0A is fabricated in UMC 55nm SP, low-k, logic process to enable size reduction and utilizes an 8-bit Programmable Gain Amplifier (PGA) with a 2:1 input multiplexer, a 10-bit pipelined analog-to-digital converter (ADC), and a 10-bit offset correction digital-to-analog converter (DAC) to implement a signal processing solution for scanners, video and CMOS imaging applications.
Learn more about Analog Front End IP core
The pre-validated IP supports EtherCAT transmission time of less than 100 microseconds and synchronization accuracy of less than 0.1 microseconds using EtherCAT Distributed Clocks (DC), while having passed rigorous ETG.7000 Conformance and IEC 61000-4 testing to help streamline customers’ ASIC development.
Third quarter consolidated revenue reached NT$3,664 million, up 11% QoQ and 13% YoY.
To address the growing demand for intelligent sensing, Faraday has expanded its MIPI C/D Combo PHY IP portfolio on UMC’s 14nm FinFET platform. T
The alien realm of ultra-low voltage (ULV) in chip design means supply voltages near or below transistor threshold voltages.
Second quarter consolidated revenues were NT$3,314 million, up 28% QoQ but down 27% YoY.
