28nm HPC x4 lane 10 Gbps SERDES
28nm HPC x4 lane 10 Gbps SERDES
- UMC
- 28nm
- HPC
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
28nm HPC x4 lane 10 Gbps SERDES
28nm HPC x4 lane 10 Gbps SERDES
MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process
MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process
CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process
MIPI Transmitter CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process
MIPI Transmitter CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process
MIPI Receiver CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process_x005F_x000D_
MIPI Receiver CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process
UMC 0.13um HS/FSG Logic Process Ultra-slim SSTL-2 (ClassI)/LVTTL (10mA) Combo I/O Cells
UMC 0.13um HS/FSG Logic Process Ultra-slim SSTL-2 (ClassI)/LVTTL (10mA) Combo I/O Cells
Analog part of 600Mbps to 4Gbps 8-lane V-By-One transmitter with embedded PLL circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process.
28nm HPC+ USB3.1 gen2 PHY(10Gbps)
28nm HPC+ USB3.1 gen2 PHY(10Gbps)
28nm HPC USB3.1 gen2 PHY(10Gbps)
28nm HPC USB3.1 gen2 PHY(10Gbps)
USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process
USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process
USB 2.0 On-The-Go PHY; UMC 40nm Logic LP/RVT Low-K Process
USB 2.0 On-The-Go PHY; UMC 40nm Logic LP/RVT Low-K Process
USB 2.0 On-The-Go PHY; UMC 28nm HPC+ RVT Logic Process
USB 2.0 On-The-Go PHY; UMC 28nm HPC+ RVT Logic Process
USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF
USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF
USB 2.0 On-The-Go PHY, analog part ; UMC 28nm HPC RVT Logic Process
USB 2.0 On-The-Go PHY, analog part ; UMC 28nm HPC RVT Logic Process
28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process
28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process
UMC 28nm HPC+, 4-Lane 1.25~12.5 Gbps SERDES
UMC 28nm HPC+, 4-Lane 1.25~12.5 Gbps SERDES
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process.
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process.
ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process
ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process
MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process
MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process