LVDS Receiver IP, 20MHz - 135MHz , UMC 0.18um G2 process
DLL-based LVDS RX, VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation frequency, UMC 0.13um HS FSG Logic process.
- UMC
- 180nm
- G
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
LVDS Receiver IP, 20MHz - 135MHz , UMC 0.18um G2 process
DLL-based LVDS RX, VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation frequency, UMC 0.13um HS FSG Logic process.
10/100 Ethernet PHY IP, UMC 65nm SP process
10/100 Base-TX Fast Ethernet PHY, UMC 65nm SP/RVT Low-K Logic process.
10/100 Ethernet PHY IP, Energy Efficient, UMC 0.11um HS/AE process
10/100 Base-TX/FX Energy Efficient Ethernet PHY, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process.
USB 1.1.OTG PHY IP, OTG, UMC 90nm SP process
USB 1.1 OTG PHY, UMC 90nm SP/RVT Low-K Logic process.
USB 1.1.OTG PHY IP, OTG, UMC 65nm SP process
USB 1.1 On-The-Go PHY, UMC 65nm SP/HVT Logic Low-K process.
USB 2.0 OTG PHY IP, UMC 0.13um LL/FSG process
USB 2.0 On-The-Go PHY, UMC 0.13um LL process.
USB 1.1.OTG PHY IP, OTG, UMC 0.25um Logic process
USB 1.1 On-The-Go transceiver (ECN spec), UMC 0.25um Logic process.
SATA II PHY IP, Gen-2, 1 - port, UMC 0.18um G2 process
1.5G/3.0Gbps 1 port Serial ATA PHY and ESATA, UMC 0.18um GII Logic process.
LVDS Transmitter IP, Tx IO, UMC 55nm SP process
0.18um TX PAD, UMC 0.18um Logic RVT-FSG process.
USB 1.1.OTG PHY IP, OTG, UMC 0.15um SP process
USB 1.1 On-The-Go transceiver, UMC 0.15um SP Logic process.
USB 1.1 PHY IP, UMC 0.15um SP process
USB 1.1 PHY, UMC 0.15um SP Logic process.
USB 2.0 OTG PHY IP, UMC 0.13um HS/FSG process
USB 2.0 On-The-Go PHY, UMC 0.13um HS/FSG Logic process.
USB 1.1.OTG PHY IP, OTG, UMC 0.13um SP/FSG process
USB 1.1 On-The-Go transceiver, UMC 0.13um SP/FSG Logic process.
USB 1.1 PHY IP, UMC 0.13um HS/FSG process
USB 1.1 PHY, UMC 0.13um HS/FSG Logic process.
SATA II PHY IP, Gen-2, UMC 0.13um HS/FSG process
Serial ATA (SATA) physical layer that provides a range of host and device functions, UMC 0.13um HS/FSG Logic process.
SATA II PHY IP, Support SATA Gen1 1.5Gb/s and SATA Gen2 3.0Gb/s, UMC 0.18um Logic process
Single channel serial ATA PHY layer compliant with SATA spec.
USB 1.1.OTG PHY IP, OTG, UMC 0.18um G2 process
USB 1.1 On-The-Go transceiver (ECN spec), UMC 0.18um GII Logic process.
MIPI On-Die Termination ; UMC 28nm HPC process
IP