Two Port Register File Compiler IP, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG Logic process Synchronous Two Port Register File with 339cell memory compiler.
- UMC
- 110nm
- HS
Embedded memory IP cores are fundamental components in modern SoC and ASIC designs, providing fast and efficient on-chip data storage for processors, accelerators, and peripherals.
These IP cores encompass a broad range of volatile and non-volatile memory technologies, including SRAM for high-speed data storage, ROM for fixed program and boot code storage, register files for processor and accelerator architectures, as well as EEPROM, eFuse/OTP, and MTP (Multiple-Time Programmable) memories for configuration data, security credentials, device calibration, and permanent system information.
This catalog allows you to compare embedded memory IP cores from leading vendors based on density, access time, power consumption, and process node compatibility.
Whether you are designing high-performance processors, AI accelerators, automotive systems, or IoT devices, you can find the right embedded memory IP for your design.
Two Port Register File Compiler IP, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG Logic process Synchronous Two Port Register File with 339cell memory compiler.
Two Port Register File Compiler IP, UMC 0.11um LL process
UMC 0.11um AE/LL eFlash process Two Port Register File.
One Port Register File Compiler IP, UMC 90nm LL process
UMC 90nm low leakage Low-K RVT process synchronous One Port Register File memory compiler.
One Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm Standard Performance Low-K Logic process synchronous Single Port Register File SRAM using 0.425-Bit cell memory compiler.
One Port Register File Compiler IP, Bit-cell: 0.425um2 (HVT), UMC 55nm LP process
UMC 55nm LP Logic process 0.425um2-Bit cell One Port Register File memory compiler.
One Port Register File Compiler IP, UMC 55nm eFlash process
UMC 55nm eFlash with peripheral HVT One Port Register File.
One Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP Logic process Single Port Register File memory compiler with LVT peripheral.
One Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/HVT Logic process with 6TSRAM (0.242 mm2) 1-port Register File memory compiler.
One Port Register File Compiler IP, UMC 0.13um CIS process
UMC 130nm CMOS Image SensorCu process One Port Register File compiler.
One Port Register File Compiler IP, UMC 0.11um SP/AE process
UMC 0.11um SP/AE Logic process Synchronous One Port Register File memory compiler with 1.41um2-Bit cell.
One Port Register File Compiler IP, UMC 0.11um LL process
UMC 0.11um AE/LL eFlash process One Port Register File.
One Port Register File Compiler IP, UMC 0.11um LL/AE process
UMC 0.11um LL/AE (AL Enhancement) Logic process 1.41um2 cell Single Port Register File (One Port Register File) memory compiler.
One Port Register File Compiler IP, UMC 0.11um HS/AE process
UMC 0.11um AE eFlash HS process for One Port Register File compiler.
One Port Register File Compiler IP, UMC 0.11um HS/AE process
UMC 0.11um HS/AE (AL Enhancement) Logic process 1.41um2 cell One Port Register File memory compiler.
Single Port SRAM Compiler IP, Support Repair Features, UMC 90nm CIS process
Single Port SRAM, UMC 90nm CMOS Image Sensor Image Sensor process.
Single Port SRAM Compiler IP, UMC 90nm CIS process
UMC 90nm CMOS Image Sensor process 1P3M Single Port SRAM compiler.
Single Port SRAM Compiler IP, UMC 90nm LL process
UMC 90nm LL Low-K RVT process synchronous Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, Support Repair Features, UMC 80nm HV process
UMC 80nm HV process Single Port SRAM memory compiler with Redundancy.
Single Port SRAM Compiler IP, UMC 80nm HV process
UMC 80nm HV process Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process
UMC 55SP Single Port SRAM with row redundancy.