Dual Port SRAM Compiler IP, UMC 0.11um SP process
UMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous High-density Dual Port SRAM memory compiler.
- UMC
- 110nm
- SP
Embedded memory IP cores are fundamental components in modern SoC and ASIC designs, providing fast and efficient on-chip data storage for processors, accelerators, and peripherals.
These IP cores encompass a broad range of volatile and non-volatile memory technologies, including SRAM for high-speed data storage, ROM for fixed program and boot code storage, register files for processor and accelerator architectures, as well as EEPROM, eFuse/OTP, and MTP (Multiple-Time Programmable) memories for configuration data, security credentials, device calibration, and permanent system information.
This catalog allows you to compare embedded memory IP cores from leading vendors based on density, access time, power consumption, and process node compatibility.
Whether you are designing high-performance processors, AI accelerators, automotive systems, or IoT devices, you can find the right embedded memory IP for your design.
Dual Port SRAM Compiler IP, UMC 0.11um SP process
UMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous High-density Dual Port SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.11um LL process
UMC 0.11um low leakage Logic process synchronous high density Dual Port SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.11um eFlash/LL process
UMC 0.11um eFlash LL process Dual Port SRAM compiler.
Dual Port SRAM Compiler IP, UMC 0.11um eFlash/HS process
UMC 0.11um eFlash HS process, Dual Port SRAM compiler.
Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm eHV process
UMC 55nm eHV process, Dual Port SRAM compiler with row redundancy option.
Dual Port SRAM Compiler IP, High density, (2RW), UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process high density synchronous Dual Port (2RW) SRAM memory compiler.
ROM Compiler IP, UMC 90nm CIS process
UMC 90nm CMOS Image Sensor process 1P3M Via ROM compiler.
ROM Compiler IP, UMC 55nm LP process
UMC 55nm LP Logic process Via1 ROM memory compiler.
ROM Compiler IP, UMC 55nm eHV process
UMC 55nm eHV PeriHVT Via1 ROM compiler.
ROM Compiler IP, UMC 55nm eFlash process
UMC 55nm eFlash process with peripheral HVT Pcode ROM compiler.
ROM Compiler IP, UMC 40nm LP process
UMC 40 LP/RVT Low-K Logic process Via1 ROM memory compiler.
ROM Compiler IP, UMC 0.18um LL process
UMC 0.18um low leakage(LL) Logic process synchronous Via1 ROM memory compiler.
ROM Compiler IP, UMC 0.13um CIS process
UMC 0.13um CMOS Image SensorCu process ROM compiler.
ROM Compiler IP, UMC 0.11um CIS process
UMC 0.11um CMOS Image Sensor process 1P3M VIA1 ROM memory compiler.
ROM Compiler IP, UMC 0.11um EEPROM process
UMC 0.11um EE2PROM/LL process PCode ROM compiler.
ROM Compiler IP, UMC 0.11um LL process
UMC 0.11um AE/LL eFlash process Via1 ROM compiler.
ROM Compiler IP, UMC 0.11um LL process
UMC 0.11um EE2PROM AE LL process Pcode ROM.
Two Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm Standard Performance Low-K process Two Port SRAM Register File compiler.
Two Port Register File Compiler IP, UMC 55nm LP process
UMC 55nm LP Logic process Synchronous Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic Two Port Register File memory compiler.