TSMC IP Cores

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.

• TSMC
• 12nm
• FFC

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.

• TSMC
• 12nm
• FFC

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.

• TSMC
• 12nm
• FFC

HCLTech offers IP Bandgap (BGR) bgr_1p2_t40_v1 generates precision reference voltage (0.4V ~ 1.2V) and current reference (1.005µA…

• TSMC
• 40nm
• G

HCLTech offers IP RC Oscillator core consists of digital to analog current converter [IDAC], Ring Oscillator and Level shifter.

• TSMC
• 40nm
• G

HCLTech offers SAR ADC 10bit hcl_saradc_10bit_5msps_t40_v1 is a general-purpose analog to digital converter (ADC).

• 10 Bit
• TSMC
• 40nm
• G

HCLTech offers IP Temperature Sensor hcl_tempsense_t40_v1 (temperature sensor IP) utilizes a Proportional to Absolute Temperature…

• TSMC
• 40nm
• G

HCLTech offers IP POR hcl_por_t40_v1 circuit provides a reset signal to the chip when supply ramps up so that the chip always sta…

• TSMC
• 40nm
• G

HCLTech offers A low drop-out (LDO) voltage regulator has been designed in a 40nm tsmc technology.

• TSMC
• 40nm
• G

HCLTech Offers IP Process Monitor IP (hcl_procmon_t40_v2) consists of three ring oscillators namely RVT Ring Oscillator, Thick ox…

• TSMC
• 40nm
• G

This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps.

• TSMC
• 28nm

The low voltage Standard Cell Library for the TSMC N3P process represents a breakthrough in power efficiency for high performance…

• TSMC
• 3nm
• N3P
• Pre-Silicon

The Synopsys Foundation IP optimized for the TSMC’s 22nm Ultra Low Leakage (ULL) process provides designers an extensive offering…

• TSMC
• 22nm
• ULL
• Available on request

Bandgap Voltage Reference, 0.45 V Output The Bandgap Voltage Reference IP is a 1.0 V input, low PPM/°C, 0.45 V reference voltage …

• TSMC
• 3nm
• N3P
• Silicon Proven

LDO Voltage Regulator, 250 mA, Adjustable 0.45 V to 0.9 V Output The LDO IP is a 1.2V low-quiescent-current adjustable output vol…

• TSMC
• 3nm
• N3P
• Silicon Proven

LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output The LDO IP is a 1.2V low-quiescent-current adjustable output volt…

• TSMC
• 3nm
• N3P

The AT256X16T152LP0AA is organized as 256 bits by 16 one-time programmable in 16-bit read and 1-bit program modes.

• TSMC
• 152nm
• G
• Silicon Proven

The ATO00128X8TS055ULP3NA is organized as 128x8 one-time programmable (OTP) in 8-bit read and 1-bit program modes.

• TSMC
• 55nm
• GP
• Silicon Proven

The ATO0001X32TS180SGE3NA is organized as 1 by 32 bits one-time programmable (OTP).

• TSMC
• 180nm
• BCDG2
• Silicon Proven

The ATO0768X39TS055ULP4NA is organized as 768x39 one-time programmable (OTP).

• TSMC
• 55nm
• ULP
• Silicon Proven