112G Ethernet LRM PHY, TSMC N3P x4, North/South (vertical) poly orientation
The 112G Ethernet PHY IP, an integral part of the 400GbE/800GbE Ethernet solution enables long reach (LR), medium reach (MR), ver…
USB-C 3.1/DP TX PHY for TSMC 7FF, North/South Poly Orientation
The USB 3.1 PHY IP provides designers with the industry's best combination of low area and low power with support for the process…
USB-C 3.1/DP TX PHY for TSMC 16FFC, North/South Poly Orientation
The USB 3.1 PHY IP provides designers with the industry's best combination of low area and low power with support for the process…
USB-C 3.1/DP TX PHY for TSMC 12FFC, North/South Poly Orientation
The USB 3.1 PHY IP provides designers with the industry's best combination of low area and low power with support for the process…
DisplayPort 1.4 TX PHY, TSMC N7, North/South Poly Orientation
The USB-C 3.1/DisplayPort 1.4 IP solution consists of USB-C 3.1/DisplayPort 1.4 PHYs, USB-C 3.1/DisplayPort 1.4 controllers (Devi…
DisplayPort 1.4 TX PHY, TSMC N4P, North/South Poly Orientation
The USB-C 3.1/DisplayPort 1.4 IP solution consists of USB-C 3.1/DisplayPort 1.4 PHYs, USB-C 3.1/DisplayPort 1.4 controllers (Devi…
DisplayPort 1.4 TX PHY, TSMC 16FFC, North/South Poly Orientation
The USB-C 3.1/DisplayPort 1.4 IP solution consists of USB-C 3.1/DisplayPort 1.4 PHYs, USB-C 3.1/DisplayPort 1.4 controllers (Devi…
DisplayPort 1.4 TX PHY, TSMC 12FFC, North/South Poly Orientation
The USB-C 3.1/DisplayPort 1.4 IP solution consists of USB-C 3.1/DisplayPort 1.4 PHYs, USB-C 3.1/DisplayPort 1.4 controllers (Devi…
Die-to-Die, High Bandwidth Interconnect PHY Ported to TSMC N7 X24
The High-Bandwidth Interconnect PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for…
The XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in mult…
The XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in mult…
The XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in mult…
The XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in mult…
UCIe-S PHY for Standard Package (x16) in TSMC N6, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-S PHY for Standard Package (x16) in TSMC N4P, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-A PHY for Advanced Package (x64) in TSMC N3E, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-S PHY for Standard Package (x32) in TSMC N3P, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
graphics, high-performance computing (HPC) and networking applications are requiring more memory bandwidth to keep pace with the …
graphics, high-performance computing (HPC) and networking applications are requiring more memory bandwidth to keep pace with the …