MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 12 FFC
Several production nodes employ C-PHY/D-PHY Combo with the least amount of power and expense.
MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 12 FFC
C-PHY/D-PHY Combo in various process nodes with low power and cost.
MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 7 FF
Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes.
MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 7 FF
Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 40LP
The D-PHY specification, version 1.2, is fully complied with by the MIPI D-PHY Analog RX IP Core.
MIPI D-PHY Tx IP, Silicon Proven in TSMC 40LP
The MIPI D-PHY Analog TX IP Core fully complies with version 1.2 of the D-PHY specification.
HDMI, LVDS, RF and Analog Pads in TSMC 45/40nm
A 1.0V to 5V Analog I/O library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in TSMC 45/40nm HPM process.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 16FFC
The MIPI D-PHY RX IP Core fully adheres to the D-PHY specification, version 1.2.
MIPI D-PHY Tx IP, Silicon Proven in TSMC 16FFC
The MIPI D-PHY Tx IP Core is fully compliant with the D-PHY specification, version 1.2, ensuring adherence to industry standards.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 12FFC
Several production nodes employ C-PHY/D-PHY Combo with the least amount of power and expense.
MIPI D-PHY Tx IP, Silicon Proven in TSMC 12FFC
C-PHY/D-PHY Combo in various process nodes with low power and cost.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 7FF
Various manufacturing nodes using C-PHY/D-PHY Combo at minimal cost and power.
MIPI D-PHY Tx IP, Silicon Proven in TSMC 7FF
Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes.
USB 2.0 PHY IP, Silicon Proven in TSMC 90G
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for exceptional performance and low power consumption.
USB 2.0 PHY IP, Silicon Proven in TSMC 65LP
A physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP.
USB 2.0 PHY IP, Silicon Proven in TSMC 55LP
In order to deliver great performance and use little power, the whole physical layer (PHY) IP solution for USB 2.0 was developed.
USB 2.0 PHY IP, Silicon Proven in TSMC 12FFC
The whole physical layer (PHY) IP solution for USB 2.0 was designed for outstanding performance and low power consumption.
USB 2.0 PHY IP, Silicon Proven in TSMC 7FF
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for exceptional performance and low power consumption.
USB 3.0 PHY IP, Silicon Proven in TSMC 55LP
For auxiliary devices, a Universal Serial Bus (USB) transceiver is offered.
USB 3.0 PHY IP, Silicon Proven in TSMC 40LP
A Universal Serial Bus (USB) transceiver is available for auxiliary devices.