VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell (05) Library developed by VeriSilicon supports power/ground pads, bi-directio…
VeriSilicon SMIC 0.13um 1.2V/3.3V OSC IO
Optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13μm Logic Salicide 1.2/3.3V process, S13V25_OSCIO_0…
SMIC 0.13µm 5V-3.3V 350mA Synchronous Buck DC-DC
The IP is a high efficiency, low ripple, current mode buck switching regulator with internal synchronous MOS switches, eliminatin…
SMIC 0.13um 12Bit 500Ksps R2R DAC
S13V33_R2RDAC_04 is a 12Bit 500Ksps DAC IP.
SMIC 65nm 1.2v/2.5v Spread Spectrum PLL
This IP is a programmable Analog PLL suitable for high speed clock generation.
SMIC 65nm Low Leakage LVDS Receiver
The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core…
VeriSilicon SMIC 0.18µm 1.8V/3.3V VPPIO_01 IO Library
VeriSilicon SMIC 0.18um 1.8V/3.3V VPPIO_01 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing Inter…
SMIC 0.18um 11Bit 500Ksps R2R DAC
SMIC18_R2RDAC_04 is a 11Bit 500KHz DAC IP.
SMIC 0.13um 2.4V Power on Reset
The present Power on Reset IP generates system reset signal (POR18, low level reset) when 3.3v power supplier (VIN18) is turned o…
SMIC 0.13um 3.3V-1.8V 360mA Synchronous Buck DC-DC
The IP is a high efficiency, low ripple, current mode buck switching regulator.
SMIC 65nm LL 3.3V-2.5/1.2V Power Regulator
This IP is a Low-Dropout (LDO) 3.3V to 2.5V and 1.2V power regulator in SMIC 65nm LL 1.2V/2.5V process.
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
SMIC 65nm 2.5/1.2V 32768Hz Crystal Oscillator
This is a 32768Hz crystal oscillator specifically designed for ultra-low power application.
SMIC 65nm LL 12-Bit 8-Input 1M/200k SAR ADC
This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution.
SMIC 0.13µm 5v-3.3v Power Regulator
This IP is a Low-Dropout (LDO) 5V to 3.3V power regulator in SMIC 0.13μm 3.3V/1.2V Logic process.
This IP is a programmable Analog PLL suitable for high speed clock generation.
SMIC 65nm USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
The present IP is a VCC Detector (VDT) circuit which detects the voltage level of its power supply, AV18.
SMIC 0.18um 3.3V Trimming Block
This IP is suitable for voltage trimming.