Samsung 8LPU 1.8V/3.3V SD/eMMC PHY AP1
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
- Samsung
- 8nm
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
Samsung 8LPU 1.8V/3.3V SD/eMMC PHY AP1
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
Samsung 5LPE 1.8V/3.3V SD/eMMC PHY AP2
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
PCI Express Gen5 SERDES PHY on Samsung 8LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen4 SERDES PHY on Samsung 7LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3/Enterprise Class SERDES PHY on Samsung 28LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3/4 Enterprise Class SERDES PHY on Samsung 14LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3 SERDES PHY on Samsung 28LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
PCI Express Gen3 / SATA3 SERDES PHY on Samsung 28FDSOI
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
LVDS Driver/Buffer
LVDS Receiver
LVDS Transmitter
Samsung 28nm FDSOI USB3.0 and PCIE2 combo PHY
The USB3.0 Super-Speed / PCI Express Combo PHY is a programmable IP that is compatible with the PHY Interface for PCI Express and…
SAMSUNG 28nm FDSOI USB2.0 Dual Role PHY/OTG PHY
The USB 2.0 OTG PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
Samsung 28nm FDSOI USB3.0 Type-C PHY
IP
Samsung 28nm FDSOI 1.8v/1.0v LVDS Transmitter
IP
Samsung 28nm FDSOI 1.8v/1.0v sub-LVDS Receiver
IP