Vendor: SmartDV Technologies Category: FlexRay

FlexRay Verification IP

FlexRay Verification IP provides an smart way to verify the FlexRay component of a SOC or a ASIC.

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Overview

FlexRay Verification IP provides an smart way to verify the FlexRay component of a SOC or a ASIC. The SmartDV's FlexRay Verification IP is fully compliant with standard FlexRay 3.0.1 (plus addendum) Specification and supports all the frame types such as Static and Dynamic frames.Also supports all operating modes such as STANDBY,NOCE,STARTUPFRAMECAS,STARTUPFRAME and SINGLESLOT modes.

Flexray 3.0.1 Verification IP includes an extensive test suite covering most of the possible scenarios. It can perform all protocal tests and moreover it allows an easy generation of very high number of patterns and a set of specified patterns to stress the DUT.

FlexRay Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

FlexRay Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Fully compatible with FlexRay specification version 3.0.1.
  • Support Full Duplex of operations.
  • Complete FlexRay Tx/Rx functionality.
  • Supports cluster wakeup and startup.
  • Transmit and receive commands allow the user to transmit and receive FlexRay data.
  • Operates as a Tx or as a Rx.
  • Supports 2.5, 5 and 10 Mbit/s bitrate.
  • Support Bit alignment
  • All types of frame generation.
    • Static frames
    • Dynamic frames
  • Various kinds of Tx and Rx errors insertion and detection.
  • Syntax errors
    • Frame ID error (Frame ID = 0)
    • Header CRC error
    • CRC error
    • Over and undersize errors
  • Content errors
    • Cycle Count error
    • Frame ID error
    • Startup, Sync & Null frame errors w.r.t Dynamic segment
    • Startup & Sync frame errors w.r.t Static segment
    • Reception of Null frame
    • Aborting in middle of transaction
  • Configurable receive FIFO depth
  • Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Supports constraints randomization.
  • Supports glitch insertion and detection.
  • Status counters for various events on bus.
  • Callbacks in Tx,Rx and monitor for various events.
  • FlexRay Verification IP comes with complete testsuite to test every feature of FlexRay specification.
  • Functional coverage for complete FlexRay features.

Block Diagram

FlexRay VIP block diagram

Benefits

  • Faster testbench development and more complete verification of FlexRay designs.
  • Easy to use command interface simplifies testbench control and configuration of TX and RX.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the FlexRay testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
FlexRay VIP
Vendor
SmartDV Technologies
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

Learn more about FlexRay IP core

FlexRay - The Hardware View

FlexRay is an upcoming networking standard being established to raise the data rate, reliability, and safety of the automotive applications of today and tomorrow. Synthesizable FlexRay intellectual property (IP) is now available for those who want to integrate it into a new chip. This paper discusses what the FlexRay IP is and how to implement it; highlighting issues, considerations, and solutions for the system designer.

e Verification Environment for FlexRay Advanced Automotive Networks

FlexRay is the vehicle networking standard being backed by all major automotive manufacturers because it is fast and flexible while being reliable and deterministic. NXP (formerly Philips) Semiconductor is a founding member of the FlexRay Consortium and has invested heavily in a comprehensive e verification environment for FlexRay, which IPextreme is taking to market.

Open Source FlexRay Communication: Time Triggered OS and FlexRay Communication Middleware

We developed a set of software programs for FlexRay communication, which is considered the next de facto standard for automotive communication, and we will release our programs as open source software in near future. For the programs mentioned above, we have decided to develop specifications for a time triggered real time operating system that is suitable for FlexRay communication middleware. This operating system has a special feature which manages both time triggered control and event triggered control

Five steps to FlexRay

FlexRay comes onto the road with single-channel high-speed power-train, driver-assistance, and comfort automotive electronics applications. In developing FlexRay applications, there are five basic steps that design engineers can apply leading to a robust network topology.

Frequently asked questions about FlexRay IP cores

What is FlexRay Verification IP?

FlexRay Verification IP is a FlexRay IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this FlexRay?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this FlexRay IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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