The vendor provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (US…
The vendor provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0 specifications. The eUSB2 PHY IP has industry's best combination of low area and low power in leading process technologies from 7nm and below.
The eUSB2 IP is built on years of customer successes with the vendor’s silicon-proven USB PHY product line, which has been ported to over 100 process nodes ranging from 180nm to 5nm.
With over 3,000 design wins and over 4 billion silicon-proven units shipped, the vendor’s USB IP solution, consisting of digital controllers, PHYs, IP subsystems, and verification IP, enables designers to lower integration risk and speed time-to-market.
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 3nm | N3E | — |
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eUSB 2.0 PHY - TSMC N3E x1, North/South (vertical) poly orientation is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.