eDP1.4/DP1.4 TX IP PHY
eDP/DP_TX consists of electrical sub-blocks of main-link and AUX channel of PHY for eDP/DP TX.
Overview
eDP/DP_TX consists of electrical sub-blocks of main-link and AUX channel of PHY for eDP/DP TX. eDP/DP_TX supports 1 or 2 lanes at 1.62Gbps(RBR) or 8.1Gbps(HBR3) for the main link, and one lane up to 1Mbps for the AUX channel.
Key features
- eDP/DP v1.4a compliant Physical layer for Tx
- Consists of two main link channels and one AUX channel
- Supports 1.62Gbps(RBR) to 8.1Gbps(HBR3) bit rate
- Supports main link operation with 1, 2 and 4 lanes.
- Integrated 100-ohm termination resistors with common-mode biasing.
- Integrated equalizer with tunable strength.
- Configurable analog characteristics
Specifications
Identity
Provider
Learn more about Single-Protocol PHY IP core
Design IP Faster: Introducing the C~ High-Level Language
Universal Flash Storage: Mobilize Your Data
Can MIPI and MDDI Co-Exist?
Enter the Inner Sanctum of RapidIO: Part 1
Networking software key to PICMG 2.16 optimization
Frequently asked questions about Single-Protocol PHY IP
What is eDP1.4/DP1.4 TX IP PHY?
eDP1.4/DP1.4 TX IP PHY is a Single-Protocol PHY IP core from Silicon Library Inc. listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.