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Philippe Luc, Codasip
Vendor:
Codasip
Category:
CPU
Dual-issue Linux-capable RISC-V core
The A730 is a dual-issue, in-order, 64-bit application processor capable of running Linux.
Overview
The A730 is a dual-issue, in-order, 64-bit application processor capable of running Linux. The core is compatible with the RISC-V RVA22 profile. The core includes a hardware floating point unit, L1 data & instruction caches, an L2 cache and an MMU. Tessent trace is available as an option.
The core supports wait for interrupt (WFI) and non-maskable interrupts (NMI) and works with a platform-level interrupt controller (PLIC). It has an AXI-5 128-bit bus interface.
The A730 core has a wide range of configuration options.
The core supports wait for interrupt (WFI) and non-maskable interrupts (NMI) and works with a platform-level interrupt controller (PLIC). It has an AXI-5 128-bit bus interface.
The A730 core has a wide range of configuration options.
Key features
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
- Dual-issue superscalar
- In-order 7-9 stage pipeline
- Interrupt controller options
- WFI
- NMI
- PLIC
- Dynamic jump prediction
- FPU
- L1 data and instruction caches
- L2 cache
- MMU
- On-chip debugger
- Optional trace
Block Diagram
Codasip A730 block diagram
Benefits
- Standards compliance
- RISC-V RVA22 profile
- Code density
- Zc extensions
- High configurability with Codasip Studio
Applications
- Communications
- Industrial electronics
- Automotive
- Consumer electronics
- Wearables
- Advanced cameras
What’s Included?
- Hardware development kit (HDK)
- Human-readable System Verilog RTL
- Synthesis scripts
- Simulation testbenches
- Debug support
- Software development kit (SDK)
- GCC C-compiler
- Assembler
- Disassembler
- Linker
- Instruction-accurate simulator
- Cycle-accurate simulator
- Profiler
- Options for configuring A730
- CodAL model for Codasip Studio
- Full-feature Studio tool for configuring A730 core
Specifications
Identity
Part Number
Codasip A730
Vendor
Codasip
Type
Silicon IP
Compute
CPU Architecture
RISC-V
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Germany
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Frequently asked questions about CPU IP cores
What is Dual-issue Linux-capable RISC-V core?
Dual-issue Linux-capable RISC-V core is a CPU IP core from Codasip listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.