Vendor: Codasip Category: CPU

Dual-issue Linux-capable RISC-V core

The A730 is a dual-issue, in-order, 64-bit application processor capable of running Linux.

RISC-V View all specifications

Overview

The A730 is a dual-issue, in-order, 64-bit application processor capable of running Linux. The core is compatible with the RISC-V RVA22 profile. The core includes a hardware floating point unit, L1 data & instruction caches, an L2 cache and an MMU. Tessent trace is available as an option.
The core supports wait for interrupt (WFI) and non-maskable interrupts (NMI) and works with a platform-level interrupt controller (PLIC). It has an AXI-5 128-bit bus interface.
The A730 core has a wide range of configuration options.

Key features

  • 64-bit RISC-V core
  • RVA22 profile
  • Linux capable
  • Dual-issue superscalar
  • In-order 7-9 stage pipeline
  • Interrupt controller options
    • WFI
    • NMI
    • PLIC
  • Dynamic jump prediction
  • FPU
  • L1 data and instruction caches
  • L2 cache
  • MMU
  • On-chip debugger
  • Optional trace

Block Diagram

Codasip A730 block diagram

Benefits

  • Standards compliance
    • RISC-V RVA22 profile
  • Code density
    • Zc extensions
  • High configurability with Codasip Studio

Applications

  • Communications
  • Industrial electronics
  • Automotive
  • Consumer electronics
  • Wearables
  • Advanced cameras

What’s Included?

  • Hardware development kit (HDK)
    • Human-readable System Verilog RTL
    • Synthesis scripts
    • Simulation testbenches
    • Debug support
  • Software development kit (SDK)
    • GCC C-compiler
    • Assembler
    • Disassembler
    • Linker
    • Instruction-accurate simulator
    • Cycle-accurate simulator
    • Profiler
  • Options for configuring A730
    • CodAL model for Codasip Studio
    • Full-feature Studio tool for configuring A730 core

Specifications

Identity

Part Number
Codasip A730
Vendor
Codasip
Type
Silicon IP

Compute

CPU Architecture
RISC-V

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Codasip
HQ: Germany

Learn more about CPU IP core

Codasip announces strategic pivot and divestiture

Codasip today announced a strategic evolution of its business to focus on the rapidly growing need for cyber-resilient semiconductor architectures and semiconductor System on Chips (SoCs). In conjunction with this change, Codasip is also announcing the divesture of its low-end RISC-V processor design business to a public US semiconductor company.

Codasip board initiates an expedited process to sell the company

Codasip, the European RISC-V leader, announced today an accelerated process to sell the company. Codasip has been awarded several grants and equity funding from various bodies of the European Union (EU) and national authorities totaling over €119 million, most of which is still to be received by the company in due course. In addition, the company estimates the follow-on phases of the grants will total a further €210 million for a total of €329 million, and the company is part of new consortiums and projects that can bring in an additional €51 million or more in future financing.

Frequently asked questions about CPU IP cores

What is Dual-issue Linux-capable RISC-V core?

Dual-issue Linux-capable RISC-V core is a CPU IP core from Codasip listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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