Vendor: Analog Bits Inc. Category: High-Speed

Differential Clock Receiver to CMOS on TSMC CLN3E

The Differential Clock Receiver macro addresses a large portfolio of applications.

Overview

The Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and use robust design techniques to work in noisy SoC environments, ranging from high speed communication to low power consumer applications.

The Receiver macro is implemented in Analog Bits’ proprietary architecture that uses core and IO devices at core voltage only. In order to minimize noise coupling and maximize ease of use, the Receiver incorporates signal ESD structures and a power supply ESD structure.

Key features

  • Differential clock receiver
  • Single-ended output to chip core
  • Wide Ranges of input frequencies for diverse clocking needs
  • Implemented with Analog Bits’ proprietary architecture
  • Low power consumption
  • Programmable termination
  • Built-in hysteresis
  • Spread Spectrum tracking capability
  • Requires no additional on-chip components or band-gaps, minimizing power consumption

Silicon Options

Foundry Node Process Maturity
TSMC 3nm N3E

Specifications

Identity

Part Number
Differential Clock Receiver to CMOS on TSMC CLN3E
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Frequently asked questions about High-Speed I/O Pad IP

What is Differential Clock Receiver to CMOS on TSMC CLN3E?

Differential Clock Receiver to CMOS on TSMC CLN3E is a High-Speed IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this High-Speed?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this High-Speed IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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